September 14 - 15, 2017

The Leela Palace, Bangalore, India

DVCon India 2017 Call For Abstracts

DVCon India 2017 Call For Abstracts

 VIEW THE CALL FOR ABSTRACTS

 

The Design and Verification Conference & Exhibition India (DVCon India) is a highly technical conference in India targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems, embedded systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India 2017 is patterned on the successful DVCon United States conference held for over 10 years in the Silicon Valley.

The ultimate goal of DVCon India 2017 is to boost the interest, usage and development of electronic system designs. We look forward to users sharing the various challenges and solutions adopted by various teams across the industry. DVCon India also provides a much-needed platform to promote upcoming Electronic Design Automation (EDA) and Intellectual Property (IP) standards in India. This 2-day conference is organized to invite industry practitioners to learn and share best practices on:

  • Modeling, Design and Verification of complex electronic systems at different levels of abstraction such as Virtual prototyping, Architectural Modeling, RTL, Emulation, HW acceleration, etc.
  • The application of system-level design and verification languages such as SystemC, SystemVerilog, PSL, e, VHDL etc for digital designs and Verilog-AMS for Analog Mixed Signal designs
  • Virtual Platform for Embedded Software Development
  • SoC Design Verification using the latest trends and methodologies such as UVM-SystemC, graph-based techniques, portable stimulus across block-subsystem-system all the way up to Post-Silicon
  • Architectural Exploration at the early stage and High-level Synthesis
  • The use of SystemVerilog Assertions (SVA), Property Specification Language Assertions (PSL) and Formal Verification Techniques (Model Checking)
  • Adoption of Universal Verification Methodology (UVM)
  • Leveraging on legacy methodologies based on OVM, VMM and migration to UVM
  • IP reuse, design automation and integration standards based on IP-XACT and SystemRDL
  • Low-power design and verification using the Unified Power Format (UPF)

General topic areas on Electronic System Level (ESL), Virtual Platform, Verification & Validation, Analog/Mixed-Signal, IP reuse, Design Automation, and Low-power design and verification will be highlighted in tutorials, papers, and poster sessions.

Conference attendees are primarily designers of embedded systems, electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools and IP integration solutions. The DVCon India 2016 conference attracts a highly skilled user base active in various industries focusing on research and development of automotive, aerospace, consumer, medical, and wired and wireless communication products.

Call For Abstracts - ESL Track

DVCon India 2017 solicits technically rich presentations that reflect real life experiences in using languages, standards, methods and Electronic Design Automation (EDA) tools.

The ESL track aims to accelerate the adoption of SystemC in the Semiconductor Industry. It provides a platform for the SystemC/TLM beginners and experts, ESL managers, and ESL vendors to share their knowledge, experiences and best practices about SystemC usage. Submissions are encouraged in (but not restricted to) the following topics:

  • Transaction-level modeling for system-level design (VP, Multi-core, Performance, etc.)
  • SystemC Language Development
  • Verification Techniques using SystemC-UVM and VPI/PLI, DPI Interface
  • Mixed-language environments involving SystemC and SystemVerilog/UVM
  • SystemC Analog/Mixed-Signal Extensions & Power Modeling
  • High-level synthesis using ESL languages SystemC/C++
  • System-level design techniques, flows and methodologies
  • Hardware/software/embedded co-design for early development
  • HW/SW Co-Simulation and SoC Architecture Exploration
  • Debugging Techniques and Configuration and Control in Platform Design

Call For Abstracts - DV Track

DVCon India 2017 solicits presentations that are highly technical and reflect real life experiences in using languages, standards, methods and Electronic Design Automation (EDA) tools for Design/Verification/Debug domains.

In the DV Track we are soliciting detailed abstracts from industry leaders to share their ideas, thoughts and experiences in solving some of the most complex challenges in their respective fields of work/research. This track provides a platform for the wide Design-Verification community including beginners, architects/experts, managers and EDA vendors to share their knowledge, experiences and best practices about Design-Verification. Submissions are encouraged in (but not restricted to) the following topics:

  • Using multiple HDLs and/or HVLs in a design cycle
  • Novel application of existing standard DV (Design-Verification) languages such as SystemVerilog, PSL, e, VHDL, etc.
  • Latest language developments in SystemVerilog
  • Advanced stimulus generation methods, reuse of stimulus across levels of pre/post silicon testing (portable stimulus)
  • System-on-Chip (SoC) Verification approaches to handle complexity, performance and reusability requirements including HW/SW cosin environments
  • UVM adoption, advanced techniques/features and extensions
  • Real life applications of assertions using SVA and/or PSL
  • Formal and semi-formal techniques, Assertion automation/synthesis
  • Verification process and resource management
  • Compliance and requirements-driven verification such as DO-254 standards
  • Debug automation through transaction-level debug, smart tricks to handle simulation performance issues, faster time to debug techniques
  • Low Power intent verification through standards such as UPF and related technologies
  • Usage of IPXACT and SystemRDL in design flow
  • AMS challenges in Verification, usage of custom extensions to UVM/SystemVerilog to handle AMS related complexities
  • RF/Very high-speed designs (including SerDes) related verification challenges and tricks used in practice
  • Testbench Acceleration techniques to meet modern ultra-complex chip verification challenges - case studies and experiences
  • Functional Coverage closure techniques and its testbench design implications

Important Deadlines

  • April 25, 2017 - Abstract submission deadline
  • June 14, 2017 - Accept/reject notification
  • July 14, 2017 - Final paper due
  • August 7, 2017 - Deadline to submit copyright form and draft presentation slides due for review
  • September 1, 2017 - Final presentation slides due for online proceedings

Submission Guidelines

Abstract submission will open on March 1, 2017.

To spare you the many hours of preparation associated with other paper submissions, DVCon India 2017 has the following process:

  • Submit a 500-1000 word abstract highlighting what you wish to present at DVCon India 2017. The program committee will evaluate your abstract. The deadline for abstract submission is April 25, 2017
  • Authors of exceptionally strong abstracts will be shortlisted for oral or poster presentation at the conference. They will present their work at DVCon India 2017 on September 14 or September 15.

An abstract is expected to include the following details:

  • A title.
  • Name, affiliation, address, phone number and email addresses for all authors.
  • An introduction that specifies the context and motivation of the submission.
  • A summary of the specific contributions of your work.
  • A summary that highlights results. To evaluate your contribution, you must specify some results.
  • References, if appropriate.

Your abstract can be at most two pages (exclusive of Author(s)' details). You can format it in single or double column. Provide enough details so that the Technical Program Committee can evaluate the potential quality and interest of your possible presentation at DVCon India 2017. A one-paragraph summary will not fulfill this requirement. Please note that submitted abstracts can be edited until the submission deadline of April 25, 2017. Download the abstract submission template here. 

Process For Accepted Abstracts

Authors of accepted abstracts will be expected to do the following in accordance with Conference deadlines:

  • Submit a confirmation form to confirm all paper and author details.
  • Produce a full paper for the conference proceedings. Only accepted submissions accompanied by a full paper will be in consideration for  the 'Best Paper' award.
  • Complete a copyright form.
  • Submit presentation slides for online distribution to conference attendees.

View/Download past conference proceedings

Questions? Feel free to contact support@mpassociates.com for questions on the submission process.


DV/TPC Chair Pushkar Naik, Applied Micro pnaik@apm.com
DV/TPC Co-Chair Srivatsa Vasudevan, Synopsys, Inc. Srivatsa.Vasudevan@synopsys.com
ESL/TPC Chair Swaminathan Ramachandran, CircuitSutra Technologies swaminathan.ramachandran@circuitsutra.com