Call for Short Workshops

DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C, C++, PERL, Tcl, and Python. Tools and methodologies include the use of testbench automation, portable stimulus, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS/DMS design and Portable Stimulus.

DVCon is looking for short workshops to encourage greater sponsorship participation from companies and exhibitors, especially smaller organizations at an affordable level. For these short workshops the topics need to be current, have a high-level of interest and offer strong continuing educational content.

Short Workshop sponsors reach a captive audience during the 45-minute educational sessions and could follow-up with attendees during breaks and following the event. DVCon is a highly targeted venue for engineers addressing major design and verification issues.

Submit proposals by August 15th, 2021


DVCon short workshops are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the short workshop.

Attendee expectations are high regarding topic, depth of engineering content and breadth of real-life examples. The Tutorial Chair will review final presentation materials to ensure high quality educational content.

Your proposal should be a short abstract of the short workshop, two to five paragraphs, 1,000 words maximum. The submission must include suggested presenters’ names, affiliations, and biographies.

Presentation slides need to be supplied in an electronic format in advance of the conference. Presentation slides will be distributed to the attendees in electronic format. Hard copies will not be provided.

Please indicate if this short workshop is a “hands-on” session or lecture format. Any necessary additional hardware that you may require must be provided by the short workshop organizers.


  • SystemVerilog for Verification and/or Design
  • SystemC /C/C++ Design and/or Verification of systems.
  • SoC and Software-driven Verification
  • Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
  • Coverage-driven Verification
  • High-level modeling and Synthesis challenges and Verification.
  • Low-power Design and Verification techniques
  • Secure/Encrypted IP-based SoC design methods
  • Debug for design and verification
  • Mixed-signal modeling and verification
  • Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT)
  • Functional Safety
  • Embedded software verification
  • Hardware/Software Co-development
  • Verification Productivity Methods
  • Formal Methodology and Static Analysis
  • Left-shift with Emulation and/or Prototyping technologies.
  • Post SI Debug
  • FPGA Prototyping
  • Moving from proprietary solutions to standards-based design and verification
  • Portable Stimulus
  • Applying Machine Learning (ML) techniques to address the verification challenges
  • Application based design verification challenges, techniques


  • Proposals should be 2-3 pages in length and should contain:
  • The topic and the Title, Detail about the problem statement and proposed solution/flow.
  • The issues to be discussed, including a short listing of pro and con arguments
  • Short biographies of the moderator and prospective panelists
  • Any special requirements
  • Submission via EasyChair – Submit Here


  • August 15, 2021: Proposals due. Submission via EasyChair – Submit Here
  • September 5, 2021: Accept/Reject Notification
  • October 31, 2021: All Tutorial content due for Conference Program website: tutorial title, abstract, speaker names, affiliations, and biographies
  • November 15, 2021: Final Presentation due to presenters on slides. Submission via EasyChair – Submit Here
  • November 22, 2021: Final Video due



  • 45-minute technical workshop prepared and presented by your company
  • Your company logo displayed in the background during Workshops
  • Your company logo displayed on the conference website
  • 5 free delegate registrations

COST: Rs. 100,000


December 14, 2021 — Tutorials and Panels
December 15, 2021 — Tutorials, Technical papers and Poster Session
December 16, 2021 — Panels, Technical paper sessions, poster session

More information on DVCon India can be found on

Conference Sponsored By: Accellera Systems Initiative is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process.

General Chair
Pradeep Salla
Siemens EDA

Tutorials Chair
Lokesh Babu Pundreeka
Cadence Design Systems, Inc.