September 14 - 15, 2017

The Leela Palace, Bengaluru, India

Event Details

MP Associates, Inc.

THURSDAY September 15, 11:30am - 12:10pm | Grand Ballroom
EVENT TYPE: KEYNOTE

SESSION 53
DV Keynote - Verification for Complex SOCs
Speaker:
Alok Jain - Cadence Design Systems, Inc.
Verifying a complex SoC consisting of tens of embedded cores and hundreds of IPs, with complex low power design features is a major challenge in the industry today. The focus of this keynote will be on the challenges and potential solutions for the verification of complex SoCs. Given the size and complexity of modern SoCs, tests can run for 18 - 24 hours or even more. The first challenge is the need for speed and how to get the best verification throughput. Another challenge is how to rapidly develop all the required test benches required for verifying an SoC. The test benches have to be developed in a way which can achieve good performance in both simulation and hardware acceleration. Yet another challenge is how to create all the tests required to stress the SoC under the application use cases, low power scenarios, and multi-core coherency scenarios. The tests have to be developed in a way that they can be reused across pre-silicon and post-silicon verification and validation platforms. One has to figure out how to measure verification coverage across formal, simulation, and acceleration platforms at the SoC level to know when you are done. Finally, there is the challenge of how to effectively debug across RTL, test bench, and embedded software on multiple verification platforms.




Biography: Alok Jain is a Senior Group Director in the Advanced Verification business unit at Cadence. He is serving as the R&D lead for the simulation performance program. He has a PhD in the area of Formal Verification from Electrical and Computer Engineering from Carnegie Mellon University, USA. He has around 20 years of industry experience. His expertise includes RTL functional verification, gate-level verification, coverage, metric driven verification and formal verification. He has 30+ technical papers in internal and external conferences and 10+ granted patents in the area of RTL simulation, Formal verification and transistor analysis.


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