25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.

THURSDAY September 15, 2:00pm - 3:30pm | Royal Ballroom
EVENT TYPE: ESL TUTORIAL

SESSION 56
ESL Tutorial: A Verification Methodology for High-level Synthesis – From C++/SystemC to RTL Signoff
Speaker:
Sandeep Dager - Mentor Graphics (India) Pvt. Ltd.
Organizer:
Ellie Burns-Brookens - Mentor, A Siemens Business

High-level Synthesis (HLS) has been proven to dramatically speed up simulation and reduce overall design/project times and verification is a big piece of the savings. Multiple customers are seeing 10-100X speedup in simulation time leading to faster and more complete verification. However, the deployment of HLS into mainstream corporate design flows really requires an end-to-end solution, with a verification methodology being a critical component for both the C++/SystemC design description and the generated RTL. More and more engineers are asking “How do I verify my C++/SystemC and know it’s good for synthesis? Is it possible to re-use my C++/SystemC vectors on my RTL easily? How do I close on RTL coverage? My corporate signoff requirement is 100% coverage on RTL, how long will that take to achieve? How do I perform an ECO? This tutorial will provide an overview of a high-level synthesis design and verification methodology that has been proven in customer production environments that takes the design from a C reference model through RTL coverage closure. It will highlight results from various customers on the benefits of using a unified HLS and HLV(High-level Verification) methodology in terms of overall productivity and specific metrics(performance, turn-around time of late changes in specification, time to close RTL coverage vs hand-coded RTL) on production projects.

What the tutorial will include:

  • Basics concepts of HLS
  • Overview of a High-level Design and Verification flow
  • Introduction of use of formal C property checking to verify the HLS source is clean for synthesis
  • Closing on coverage for the HLS source
  • Basic synthesis flow to perform design space exploration for area, performance, and power
  • Re-Use of high level verification model and test vectors in RTL simulation for closure
  • Using existing RTL verification tools and methodologies to close on 100% RTL coverage
  • Fundamentals of performing an ECO with HLS

 

Who should attend the tutorial:

  • Hardware engineers interested in learning about Catapult High-level Synthesis and Verification flow
  • Verification engineers interested in HLS and how to close coverage on the generated RTL
  • Engineering managers who want to understand how Catapult can fit into their existing design flow

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