25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.

THURSDAY September 15, 4:00pm - 5:30pm | Grand Ballroom

DV Tutorial: An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to Software Driven Chip Level Verification Across Simulation and Emulation

Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
Keshav Joshi - Mentor Graphics (India) Pvt. Ltd.
The increased use of processor cores, RTL reuse and software applications challenges semiconductor development schedules. Efficient and thorough RTL subsystem verification requires a coverage driven verification methodology at the block level. Verification of subsystem integration and interaction requires VIP and software driven methodology at the full chip level. Software and hardware co-simulation is required for pre-silicon software validation. Product schedules do not allow for development of separate environments for block, chip and software testing. The UVM reuse methodology presented in this tutorial provides reuse from block to chip to software testing in simulation and emulation. This open source library defines a UVM use model, provides a UVM jumpstart and includes a code generator. It has been proven across multiple industries using FPGA and ASIC.

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