September 14 - 15, 2017

The Leela Palace, Bangalore, India

Event Details

MP Associates, Inc.

THURSDAY September 15, 4:00pm - 5:30pm | Diya
EVENT TYPE: DV TUTORIAL

SESSION 64
DV Tutorial: Using Portable Stimulus for SoC Verification as Applied on Mobile, Networking, and Server Designs

Speakers:
Sandeep Gor - Cadence Design Systems, Inc.
Naresh Ramachandran - Cadence Design Systems, Inc.

Developers are facing processor architectures in a large variety of devices, from sensors through mobile and consumer devices all the way to networks and servers enabling cloud-based applications. System on chip (SoC) designs include more and more processor cores, more IP, complex power control, coherent interconnect, and complex software-controlled operations. Verification is undergoing a transformation to novel software-driven approaches, introducing unique challenges in terms of writing tests for the complex interactions at the subsystem and SoC level. Ensuring that expected performance targets are achieved is becoming more and more difficult due to the number of processors and the expanding configuration choices of system interconnect. Developing hardware and software in parallel is often facing significant barriers: Suitable models for all the IP blocks may not be available, and when they are available, they may be in RTL only, lacking corresponding transaction-level models.

The tutorial session will cover: 

  • State-of-the-art solutions to address SoC-level challenges and demonstrate a comprehensive SoC verification flow
  • Case studies where these approaches have been utilized in practice
  • Different options of hardware-assisted development
  • How best throughput for verification tasks can be achieved in emulation and FPGA-based prototyping

 

What you will learn?

  • Innovative approaches to software-driven verification, building on proven model-based software testing approaches, allowing capture system actions, pre-conditions, post conditions, and resource requirements to validate SoC-level features and generate portable stimuli including coverage analysis
  • How to achieve 10X faster SoC performance analysis and verification of ARM® CoreLink™ IP-based systems
  • How verification can be accelerated using mixed TLM-RTL execution approaches both in software simulation as well as in hardware-assisted execution of hardware/software verification

Sponsored by: