THURSDAY September 14, 12:10pm - 1:00pm | Grand Ballroom
Thirty-year old hardware emulation is enjoying a renaissance of sorts as it finds itself at the foundation of most SoC verification flows. Many reasons account for the tool's turn of luck, moving it out of dusty backrooms and into a new starring role. Its popularity is a result of numerous factors, ranging from improvements in functionality and usability to design complexity and more embedded software for each design to easier-to-use platforms.
Certainly, complexity and rising costs of doing verification forced projects groups to become more creative in their quest to thoroughly and rigorously test and debug SoC design and the expanding role of hardware/software integration. Credit, too, goes to hardware emulation vendors who re-created the notoriously difficult-to-use and expensive tool into one that's easier to use with greater flexibility, versatility and scalability. They're more attractive now as they become remote access capabilities within a data center. Use models are growing as well for more options to increase productivity and reduce verification risks.
Not too be overlooked are rapid prototyping and virtual prototyping, niche tools integrated with hardware emulators and also used to curb complexity in the chip design verification flow.
Lauro Rizzatti will act as moderator and panelists from Cypress, Mentor, A Siemens Business, Microsemi and Qualcomm will weigh-in on building an effective chip design verification flow. The result will be a lively discussion for hardware designers, software developers, verification engineers and engineering managers concerned about the growing complexity of chip design verification. The panel will review what new features were added to hardware emulation to make it a potent bug tracker, determine what else is needed and debate whether prototyping will move into mainstream verification.