RISC-V is changing the game for IP providers and SoC designers. Providers can offer commercial cores without the need to acquire expensive licenses, while open-source implementations are already available. SoC teams that want to use RISC-V processors have many choices, with even more options expected soon. The sheer number of companies and products using RISC-V guarantees a rich ecosystem and a good chance of industry disruption.
However, design integrity is a challenge for both core developers and core integrators. To be successful, IP vendors must compete against long-established processor families with decades of proven silicon. RISC-V cores must be thoroughly verified as functionally correct to satisfy the Instruction Set Architecture (ISA) and other requirements. Integrators must be certain that cores are fully compliant, and many will want to re-verify the one they choose.
Hardware Trojans or other unintended logic can be inserted at multiple points in the development process. Showing that the RISC-V core can be trusted requires proving that no such issues exist. Only formal verification has the potential to prove both ISA compliance and trust. Some types of unintentional design errors can also provide an attack gateway. Analysis of both the RISC-V core and the SoC that integrates it can prove that the design is secure.
This workshop provides guidance for RISC-V core vendors who need to verify their IP, developers of cores for internal consumption, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources. The workshop agenda is as follows:
- Challenges for RISC-V verification
- Formal specification of the ISA
- Formal verification of ISA compliance
- Detection of Trojans and malicious logic
- Detection of hardware security holes
- Examples from verification of open-source cores
- Examples from verification of open-source SoCs
- Future work and summary
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