25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
WEDNESDAY September 25, 2:00pm - 3:30pm | Robusta
EVENT TYPE: TUTORIAL
SESSION 1T
Tutorial: System Level Flows for SoC Architecture Analysis and Design

Speakers:
Swaminathan Ramachandran - CircuitSutra Technologies Pvt. Ltd.
Ajay Goyal - Infineon Technologies
Umesh Sisodia - CircuitSutra Technologies Pvt. Ltd.
Organizer:
Umesh Sisodia - CircuitSutra Technologies Pvt. Ltd.

A Case Study of Single Source Methodology for Early SoC Development

Speaker - Ajay Goyal -Infinieon Technologies

The complexity of SoC design is increasing everyday in terms of number of gates, architecture etc. Along with the increasing complexity, today’s designs have to be efficient in terms of power/performance/area. If we follow the traditional approach of design development, then meeting the above requirements within the demanding time-to-market constraints will be very challenging.

In current design development methods, design and architecture issues are identified much later in the design cycle leading to ECO (Electronic Change Order), thus affecting time to market. In this section, we will discuss multiple system level methodologies @Infineon which enables early design analysis, facilitating ‘Shift Left’. The ‘Shift Left’ approach has been introduced to domains like power intent/estimation, timing constraints checks and floor planning, thus assisting SoC architects to do ‘what-if’ analysis and make correct decisions much early in the design cycle. This approach is also extended to embedded software domain for enabling customers to develop early application software using Virtual Prototypes. 

Defining a SystemC Methdology for your Company

Speaker - Swaminathan Ramachandran - CircuitSutra Technologies Pvt. Ltd. 

As SystemC gains popularity in the fields of architecture evaluation, virtual platform development, SoC level verification etc, more teams and companies want to explore, experiment and deploy it for their modeling usecases. While SystemC library provides the vocabulary and the nuts and bolts to build a useful and diverse set of models, it is sometimes too low level to be immedidately useful. What is needed is a SystemC library analogous to Boost libraries in C++, for building blocks like memories, buses, registers, timers etc along with the infrastructure to quickly stitch them together into a working platform asap. Most of the Semiconductor companies who have successfully deployed SystemC, have developed their own tool independent methodology on top of SystemC, and they use it together with advanced modeling tools from EDA vendors. Such a library usually starts with basic building blocks, and over a period of time becomes a very rich collection of re-usable modeling components that can be re-used across various IP models, SoC variants, Modeling Use cases, Business units etc.

Any company looking to adopt SystemC in their flows should carefully conceptualize development of such a methodology inhouse, and can learn from the best practices being followed in the Industry. In this presentation we will talk about what should be the content of such a methodology/library and how it should be conceptualized.

CircuitSutra has worked with leading semiconductor companies for more than a decade now and has participated in modeling projects from the stage of experimentation to pilot projects and to widespread adoption. We have in-depth understanding of the best practices followed in the modeling domain.

Using High-Level Synthesis to migrate Software Algorithms to Semiconductor Chip designs

Speaker - Umesh Sisodia - CircuitSutra Technologies Pvt. Ltd. 

High-Level Synthesis (HLS) raises the abstraction of chip design beyond RTL. It enables implementation of design functionality in high level languages like C++/SystemC, and generates corresponding RTL using the HLS tools. Synthesizable C++/SystemC code for a design is very concise compared to resulting RTL code for the same design, and simulation of C++/SystemC models is much faster compared to RTL simulation. This allows significant productivity gains in design and verification process.  HLS also allows separation of functionality from architecture constraints and technology parameters, thus permitting code re-use across different variants of semiconductor chips, or across FPGA and ASICs.

HLS flows are more effective for algorithm centric designs. Nowadays we see new chip design requirements for emerging domains like 5G, Deep Learning, Vision, Image Processing, Speech, Audio processing etc. In these domains there are many algorithms implemented in software, and several of these are available as open source.

In this talk we will present a HLS based methodology to quickly migrate a software algorithm implemented in C/C++ to a hardware implementation in RTL for semiconductor chips (FPGA or ASIC). We will also cover a verification flow that allows use of the original testsuite of the software algorithm to verify the synthesizable C++/SystemC model as well as the final RTL. The untimed C++/SystemC models are also suitable to be used in Virtual Platforms, that allows embedded software development much before the chip is designed.

This methodology accelerates the pace of innovation, enables faster roll out of new chips, permits experimentation by quickly trying out the functionality in software and hardware, and taking high level architecture decision much earlier in the cycle.