25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
THURSDAY September 26, 4:00pm - 5:30pm | Arabica
Machine Learning & Automation
Prasanna Keshavan - HCL Technologies Limited
Automation in the VLSI project cycle provides the advantages of improving productivity and quality while reducing errors and adding flexibility to the process. In this session we have a couple of papers that talk about the automation implemented in the design flow that helped in efficiency improvement. The rise of machine learning (ML) has introduced many opportunities for computer-aided-design, VLSI design, and their intersection.  We have an interesting submission that talks about a scalable and parameterized HW architecture that can be used to build a convolutional and fully connected neural network used in ML applications

10.1Hardware Implementation of Smallscale Parameterized Neural Network Inference Engine
This paper presents a scalable and parameterized hardware architecture for convolutional and fully connected neural networks. This is a quick and low cost inference engine for verifying solutions in hardware. Architecture with four convolution operations in parallel and with parallel multiplier and adder are implemented for increased performance and larger timing margin. The architecture is easily customizable for many topologies with minimal changes. Modular architecture with parameterized design provides an excellent workbench for fast and easy neural network applications.
 Speaker: Vishnu Bharadwaj - Manipal Institute of Technology
 Authors: Vishnu Bharadwaj - Manipal Institute of Technology
Shruti Narake - Manipal Institute of Technology
Saurabh Patil - Intel
10.2Automatic Generation of Infineon Microcontroller Product Configurations
The device Configuration Sector (CFS) is a dedicated embedded Flash area to store the information on how single SoC can be configured to serve miscellaneous customer requirements and address varying markets. An Infineon microcontroller or any SoC for that matter can be configured and offered to customers. These configurations are distinguished only by small pieces of changes which goes in the embedded Flash Memory. Additionally, every delivered device is individually configured with unique chip identification, repair information and trimming values. Manual handling of the configurations is a redundant job, prone to inconsistencies due to increased complexity. The main goal of this approach is to achieve an automated flow to generate multiple product configurations using available single source data. The proposed flow allows a tighter development process connection between Marketing, Concept Engineering, Design, Firmware and Test thus ensuring consistency. We target productivity gain, reduced time-to-market and increased quality with central deployment and maintenance.
 Speaker: Prateek Chandra - Infineon Technologies
 Authors: Leily Zafari - Infineon Technologies
Boyko Traykov - Infineon Technologies
Prateek Chandra - Infineon Technologies
10.3Automation of Waiver and Design Collateral Generation for Scalable IPs
In order to achieve faster time to market for an SOC, the IP design cycle to add new features has to be shortened to the maximum extent possible. A majority of this time is used to rerun design tools and making sure the design meets the various quality guidelines. This time can be greatly reduced by writing the waivers for various design tools, RTL top file and other collaterals as templates. These templates take the IP top level parameters which are specific to each SOC as inputs and generate the design collaterals specific to them. This paper explains this technique and also analyzes the different challenges faced. Adoption of this flow would save considerable time both for the designer and the integrator of the IP.
 Speaker: Midhun Krishna - Intel
 Authors: Gopalakrishnan Sridhar - Intel
Sateesh Vadlamuri - Intel
Midhun Krishna - Intel