25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
THURSDAY September 26, 4:00pm - 5:30pm | Grand Victoria A
EVENT TYPE: REGULAR SESSION
SESSION 11
MISC-II
Chairs:
Hans van der Schoot - Mentor, A Siemens Business
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
In this “potpourri” session of papers on miscellaneous topics, verification (process) automation is the keen common thread that rings throughout to improve consistency, quality and ultimately verification productivity.  One paper vows to simplify functional coverage implementation through automated generation of a complete package of SystemVerilog coverage models that can be readily connected to your UVM testbench.  A second paper similarly focuses on accelerating functional coverage closure using a novel method for writing goal-oriented tests with smart stimulus constraint models that ensure coverage goals are reached with certainty and without redundancy.  A third paper proposes an automated approach for easier, scalable integration of verification IP and testbench components into an SoC platform.

11.1Uncover: Functional Coverage Made Easy
Functional coverage is the compass that guides one through the process of verification closure, the essential answer to, “Are we there yet?”. It is the feedback mechanism that tells what was tested, and importantly, what was missed. But, writing coverage code is often considered tedious; the reason being monotony and time consumption. The proposed flow is an attempt to make functional coverage coding hassle-free and more organized, with the following unique selling points: - Auto-generation of a complete coverage package that can be directly connected to the testbench. - An elegant shorthand notation to generate SystemVerilog coverage code, which reduces the lines of code to be written by at least 400%. - Separates manipulation of data from actual coverage collection. - Consistent implementation across projects and testbenches, with support for easy review and back annotation of results.
 Speaker: Akash S - NVIDIA Corp.
 Authors: Akash S - NVIDIA Corp.
Rahul Jain - NVIDIA Corp.
Gaurav Agarwal - NVIDIA Corp.
11.2Architecturally Scalable Testbench for Complex SoC
The SoC design complexity increases by multifold year on year. To address the growing complexity of design, it mandates the need of optimized testbench to adhere strict time to market scenarios. Also, the optimized testbench should enable concurrent verification based on the available RTL integrated blocks. The below figure explains how the transistor size increases year on year and the need of scalable Testbench. When the product portfolio increases, a generic testbench to cater all the diverse product needs is limited. Maintaining such a generic testbench becomes bulkier over a period of time. To use the generic testbench for a specific product, there arises a need to bring in the required verification components, integrate and verify this product. Integration of such verification components manually is time consuming and may lead to human errors. There arises a need for testbench components integration in a modular fashion to reduce complexity/compute time with increased efficiency. To adhere strict SoC timelines, there is a need for RTL less Testbench compile. Before receiving the first level integrated RTL, the SoC Testbench should be integrated with the required verification IP’s (VIP) based on the I/O interfaces. This enables the scope to automate the VIP integration and the number of VIP instances in the testbench instead of manual integration. Here, it enables a need for smart integration of VIP’s and its instances by automation. Re-use being the most covinent way, any manual Testbench component addition or removal will result in significant increase in time to stabilize the Testbench. This also increases the Testbench size and number of compile/run time switches. Maintaining the Testbench over a period of years become cumbersome. The Architecturally Scalable Testbench(ASTB) provides a automated way to integrate/remove any compomnent into the testbench based on the configuration, and migrate the same across different SoC platform.
 Speaker: Senthilnath Subbarayan - Qualcomm India Pvt. Ltd.
 Authors: Senthilnath Subbarayan - Qualcomm India Pvt. Ltd.
Arulanandan Jacob - Qualcomm India Pvt. Ltd.
11.3Goal Driven Stimulus Solution - Get Yourself Out of the Redundancy Trap
Functional coverage is a key metric for verification closure and constrained random simulations have become the industry practice for achieving that goal; however it does not ensure with complete certainty meeting the coverage goals, even after running multiple random seeds or increasing volume of data traffic. This paper proposes a novel method for writing goal driven tests by use of smart constraint modelling, governed by feedback for reaching the coverage goals with certainty. This approach has a number of benefits including: faster automated coverage closure, saving regression resources and associated costs, random stability concerns for derivative projects. This paper discusses practical examples of problems faced, the proposed solution and demonstrates application on live project which resulted in significant savings.
 Speaker: Rohit Bansal - Samsung Electronics Co., Ltd.
 Author: Rohit Bansal - Samsung Electronics Co., Ltd.