25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
THURSDAY September 26, 4:00pm - 5:30pm | Grand Victoria B
EVENT TYPE: REGULAR SESSION
SESSION 12
Low Power
Chair:
Ashok Natarajan - Intel Corp.
Low power design is a necessity today in all SOC’s. With the declining gate length in new process technologies, power dissipation has become a much bigger problem than what it was few years ago. As companies, started packing more and more features and applications on the battery operated devices , battery backup time became very important. Nowadays, power is replacing performance as a key competitive metric and an increasingly important criterion from the customers. In this session we have some interesting Low power design/verification techniques employed by some leading technology teams that helped solve this challenge

12.1Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design
Abstract: In the Client SoC world, IP designs are sourced from both internal and external channels and SoC team faces multiple challenges in building the bottom-up SoC UPF and in performing power aware functional verification in the hierarchical low power design flow since there are quite a few HIPs in the design which are imported with their own implementation as well as simulation models. In this paper, we will demonstrate how to replace the traditional process of building SoC UPF for hard macros with a much more efficient method by enabling power models in the hierarchical UPF. Also, this paper focusses on more accurate low power verification across all the front end flows such as static verification, power aware simulation as well as power aware emulation.
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd
 Author: Rohit K. Sinha - Intel Technology India Pvt. Ltd
12.2Low Power Techniques in Emulation
Since the design size is decreasing and designs are becoming more complex, it is difficult to add power control measures in the design. Also, the demand for low power consumption is increasing in the market, thus it is important to have low power features in the design. Consequently, power has become an important concern for the chip designers. There are different techniques for power management such as level shifters, clock gating, partitioning the design in multiple power domains, these techniques are deployed in every stage of the design to optimize the power. Thus, it is very important to check that these power management techniques work as expected and do not alter the functionality of the design. Hence, power verification techniques are very important.
 Speaker: Pragati Mishra - Arm, Ltd.
 Authors: Pragati Mishra - Arm, Ltd.
Jitendra Aggarwal - Arm, Ltd.
12.3Low Power Validation on Emulation Using Portable Stimulus Standard
 Speaker: Deepinder Mohoora - Intel Technology India Pvt. Ltd
 Authors: Deepinder Mohoora - Intel Technology India Pvt. Ltd
Joydeep Maitra - Intel Technology India Pvt. Ltd
Vikash Kumar Singh - Intel Technology India Pvt. Ltd