PCIe as a high speed and throughput bus is used frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels such as
- Application layer with verification and system performance analysis of applications, drivers and algorithms
- Transaction layer
- Data link layer for PCIe controller
- Full system design, including the PHY layer and PCS and SERDES verification
In this workshop, we will introduce 3 typical solutions that enable chip designers to meet the power, performance and area requirements and “shift-left” PCIe verification.
1. PCIe verification IP (VIP) for System/PCS/SERDES verification,
2. Virtual host PCIe solution with ZeBu emulator and,
3. Prototyping solution for system validation with HAPS
Speaker Bio: Anunay Bajaj is a Senior Applications Engineer and with close to 9 years’ experience of Functional Verification of PCI Express technology. He understands that growing design and protocol complexities demand innovative efforts to reduce verification turnaround time and thus, there continuum from Simulation to Emulation is need of the industry by default. He has led many successful PCIe customer engagements ranging from stand-alone IP level verification in pure simulation to Pre-Silicon Software development Virtualized environment.
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