25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
THURSDAY September 26, 11:30am - 1:00pm | Grand Victoria A
Amit Agarwal - NVIDIA Corp.
UVM has become first choice for verification engineers across the VLSI industry,  to create testbenches and for verifying IP’s & sub-systems. This session will provide an insight into some of the application of UVM like implementing UVM RAL coverage using prediction logic, enhancement in the inbuilt UVM_Reg model to provide additional capabilities for register/memory verification. This session will also provide a deep dive of UVM based testbench to verify LDPC (Low Density Parity Checker) Codec design. At the end of session, UVM users will get to learn about the improvements that other teams are doing over and above the existing capabilities of inbuilt UVM library and will also learn how UVM can be used effectively to achieve coverage driven verification closure

3.1Enhanced LDPC Codec Verification in UVM
Error control coding (ECC) methods are employed widely in the field of electronic communication and storage systems. ECC helps in increasing the reliability of the data when the data is corrupted by perturbation in the channel. Low Density Parity Check (LDPC) is one of such methods, robust enough to boost the reliability near to theoretical limits. This advantage of high reliability comes with a cost of complexity in decoder. LDPC decoder is generally defined as message passing or iterative algorithm [1]. Unlike the classical cyclic ECC methods, LDPC has a probabilistic error correction mechanism. Hence the verification poses lot of challenges in error pattern generation mechanism and performance evaluation. Also, optimizations in encoder design [2], needs to be completely verified for various data patterns. Listed below are the prominent challenges in full codec verification of LDPC. • Different types of random errors to be injected to verify the iterative decoder thoroughly. • Error injection and scoreboard must be portable at the sub-system verification. • Scoreboard needs to know which data patterns are correctable and which are not. It is an algorithm driven decision. • Additional support needs to be present in the scoreboard to ease the failure debug. Failure debugs are notorious as they will show up as the mismatches of few bits in the large number of data bits. • LDPC decoder has pipe-lined implementation with multiple memory blocks. Utilization of the same must be measured to optimize the design for area and performance. In the current paper, we describe the UVM test bench created to verify the LDPC codec. Significant tasks are explained in the subsequent paragraphs. Use of DPI interface is one of the important aspects of the test bench. C++ Models of encoder and decoder are integrated for enhancing the scoreboard’s capabilities. The integration of C++ model allows the scoreboard to add intermediate checkers and ease the debug by logging the necessary data from models. Scoreboard and related monitors are abstracted into another sub-environment (sub-env). This sub-env enhances the portability from unit level to sub-system level verification. Error injection mechanism is one of the interesting tasks in ECC verification. In the current test bench, it is cleanly separated out as the error configuration object. It supports not only injecting different number of errors, also errors within random window of the codeword, bursts of errors, multiple bursts of errors and biased data corruption by either corrupting only data bits containing 1s or 0s. It is divided into multiple objects and post randomization is used to create all the random errors. Based on the error injection percentage, it injects random error types, hence enabling the test bench to create numerous error scenarios. While the test bench performed full random data generation and corruption, at the same time it supports very specific error injection scenario creation. These dedicated testcases are created to visualize the critical interaction of algorithmic level logic and control logic for the codec. Random error injection at the unit level is transaction oriented. At the the sub-system, it is not acceptable as it would result in unacceptable delays. Hence slight modification were done to use all the error configuration to support live error injection at sub-system level, thereby improving the reusability Analytics has given another important dimention to the test bench, by creating statistics of various measurements. Resource utilization of memory blocks and specific logic utilization duration in the design helpd in optimizing the design for area and performance. Results • With the seeded regression, 100% code coverage was achieved. • DPI integration has reduced the effort in debugging due to the depth of information it could provide. • Sub-system integration by reuse of Scoreboard and error injection, completed within weeks of sub-system design availability. • Analytics provided the confidence required to meet the performance goals at the system level . References : [1] Introducing Low-Density Parity-Check Codes, Sarah J. Johnson School of Electrical Engineering and Computer Science ,The University of Newcastle, Australia [2] Efficient Encoding of Low-Density Parity-Check Codes, Thomas J. Richardson and Rüdiger L. Urbanke.
 Speaker: Anand Shirahatti - VerifSudha Technologies Pvt Ltd
 Authors: Anand Shirahatti - VerifSudha Technologies Pvt Ltd
Shriharsha Koila - VerifSudha Technologies Pvt Ltd
Ganesh Shetti - VerifSudha Technologies Pvt Ltd
Prateek Jain - Yoctozant Technologies Pvt. Ltd.
3.2Leveraging UVM IEEE 1800.2 for improved RAL modelling
The UVM-RAL verification environments having multiple processors or masters accessing same registers (uvm_reg_block) with dynamic address mapping could be challenging for anyone, especially when no standard solution are available in traditional UVM. As of now, the industry were solving these problems traditionally by home-grown techniques with less efficient codes and low reusable quotients. A year ago, Accellera introduced new reference implementations aligned with IEEE 1800.2 standard for UVM with many improvements and new features like dynamic (uvm_reg) mapping. This paper aims to provide IEEE 1800.2 UVM based solutions to complex register blocks or structures that cannot be modelled statically and requires multiple mapping and remapping of registers (uvm_reg) dynamically. The proposed solution would also try to accommodate any potential vertical reuse and future expansions of dynamic address mapping.
 Speaker: vikas sharma - Mentor, A Siemens Business
 Authors: vikas sharma - Mentor, A Siemens Business
Manoj Manu - Mentor, A Siemens Business
Ankit Garg - Mentor, A Siemens Business
3.3Functional-Coverage Sampling in UVM RAL: Use of 2 Obscure Methods
The UVM Register Abstraction Layer (RAL) is a very powerful feature to model the memory-mapped behavior of the registers and memories in the DUT. Based on the user's input the register-model-generators automatically generate the covergroup for the RAL functional-coverage. Depending on whether the covergroup needs to be sampled automatically on register access or as the result of an external call, two different methods need to be implemented; sample() and sample_values(). Due to the lack of information about these methods, they are rarely and improperly used. Thus, in this paper, the focus is to answer the following questions: which of the 2 methods to be used, when to be used and how to implement. Additionally, the methods are compared and contrasted, and there will be suggestions about which method could be used and their advantages in a given situation.
 Speaker: Muneeb Ulla Shariff - Mirafra Technologies
 Authors: Muneeb Ulla Shariff - Mirafra Technologies
Ravi Reddy - Roche Sequencing