25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
WEDNESDAY September 25, 2:00pm - 3:30pm | Grand Victoria A
Tutorial: Simulation Acceleration to Speed Block and Platform Level IP Verification

Prashanth Srinivasa - Synopsys, Inc.
Rajesh Kumar Meda - Synopsys, Inc.
Prashanth Srinivasa - Synopsys, Inc.

Simulation Acceleration effectively addresses the runtime performance challenges of a simulation platform, by providing a speedup of the order of 100x over simulation.
This enables user to not only find bugs quicker, but also achieve “shift left” through performance analysis, power estimation, etc much earlier in the design cycle.
User friendly features, acceleration VIPs and debug are keys for seamless integration and quicker adoption of acceleration.

In this workshop we discuss the new simulation acceleration technology with Synopsys VCS-ZEBU on the following lines:
- Reusing SystemVerilog/UVM testbenches in moving from simulation to acceleration step by step.
- Ways of finding performance bottlenecks through profiling and guidelines to improve the performance
- Debug features and effective ways of debugging a verification environment

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