25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
THURSDAY September 26, 2:00pm - 3:30pm | Arabica
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
AMS DV enables the engineers of analog and mixed signal systems and integrated circuits to create/model continuous time and event driven models for verification of complex analog, mixed signal circuits. From being used/implemented in isolated pockets, the AMS is gaining momentum at exponential pace and will be an inevitable part of DV closure/sign-off. The complex techniques used in bringing the two unique worlds of Digital and Analog together is not just challenging but time consuming as well. 

6.1Simulation Analog Fault Injection Flow for Mixed-Signal Designs
This paper proposes a methodology to perform analog fault injection simulations to fulfil the functional safety requirements in safety critical integrated circuit (IC) developments, as required for example by ISO 26262 for automotive parts.
 Speaker: Pablo Cholbi - Analog Devices, Inc.
 Authors: Pablo Cholbi - Analog Devices, Inc.
Dylan OConnor Desmond - Analog Devices, Inc.
Raman K - Analog Devices, Inc.
6.2Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs
High Speed Interface (HSI) protocols like USB, PCIE, SATA, etc. are used in a wide range of applications today from Mobiles to PCs. Most of these protocols have a dedicated Physical layer (PHY) which typically comprises of Transceiver, Clock generation and protocol handling blocks. The PHY is generally partitioned into two blocks- the Physical Coding Sub-layer (PCS) which is the protocol dependent portion and the Physical Media Attachment (PMA) Layer. Most HSI links operate on independent clocks on Host/Device ports. In addition to protocol level implementation. PCS is responsible for managing Clock Tolerance Compensation (CTC) [2] to ensure data-integrity in the Rx data-path from PMA to Link layer. . CTC necessitates implementation of a special buffer called Elastic Buffer (EB) in the receiver path to handle the frequency difference between bit rates at the two ends of a channel. The EB plays a vital role in maintaining correct and uninterrupted communication between the two link partners. The variation in Far-end and local PLL frequency results in differential write/read throughput from the EB. EB is designed to compensate for this difference and to ensure data integrity without overflow/underflow. The Elastic Buffer can operate in two modes viz. the nominal half full buffer mode and the empty buffer mode depending on how it handles SKP-insertion/removal. The paper describes about these modes briefly and discusses on the verification challenges, strategies, generation & choice of stimulus needed for stress testing the elastic buffer. It also includes the methodology used to create frequency deviation between the read and write pointers of the buffer by using SSC/PPM/jitter and covers various SKP handling scenarios and impact of regular/irregular SKP insertion on buffer operation. Finally, the paper illustrates various debugging techniques employed to analyse the buffer behaviour under these stimulus and simulation results that were obtained during the verification process.
 Speaker: Kamesh Velmail - Samsung Electronics Co., Ltd.
 Authors: Kamesh Velmail - Samsung Electronics Co., Ltd.
Suvadeep Bose - Samsung Electronics Co., Ltd.
Parag Lonkar - Samsung Electronics Co., Ltd.
Somasunder Sreenath - Samsung Electronics Co., Ltd.
6.3DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF
The demand for increased data throughput has resulted in aggressive migration to advanced process technology nodes in order to support higher operating frequencies. As a result of the smaller geometries in advanced technology nodes, the effect of cross coupling at interconnects and buses, delay/distortion of signals traveling on high-speed interconnects need to be analysed to ensure signal integrity. DDR system consists of Memory Controller, PHY and DRAM devices connected externally on the system board. Information transfer between the controller and off-chip DRAM is handled by the PHY layer of a DDR interface. In order to ensure good data-integrity of the system in silicon, the DV infrastructure needs to be enhanced. The effect of silicon artefacts like cross-coupling, noise, delay, distortion etc. need to be modelled in order to thoroughly verify the functionality of DDRPHY. Delay Network Module (DNM) has been developed to enable robust verification.
 Speaker: Tapas Ranjan Jena - Samsung Semiconductor India R&D, Bangalore
 Authors: Tapas Ranjan Jena - Samsung Semiconductor India R&D, Bangalore
Gaurav Kumar - Samsung Semiconductor India R&D, Bangalore
Gowdra Bomanna Chethan - Samsung Semiconductor India R&D, Bangalore
Sriram Kazhiyur Sounderrajan - Samsung Semiconductor India R&D, Bangalore & Samsung Semiconductor, Inc.
Somasunder Kattepura Sreenath - Samsung Semiconductor India R&D, Bangalore