THURSDAY September 26, 2:00pm - 3:30pm | Grand Victoria A
EVENT TYPE: REGULAR SESSION
Karthikeyan Subramanian - Qualcomm India Pvt. Ltd.
In this session of papers on verification infrastructure, portability and validation, you will uncover and learn about Design Patterns, these are foundations of UVM. Once the testbench infrastructure is in place, you will see how using Python one can create portable tests for both in Pre-Silicon and Post-Silicon and finally you will see how one can achieve validation of Firmware in pre-silicon simulation and also getting coverage on Firmware code.
|7.1||Using Software Design Patterns in Test Bench Development for a Multi-Layer Protocol|
|Modern day functional verification has become a very complex task with increasing design complexities and consumes almost 53% of the project time on an average as per recent studies . Coupled with faster turnaround times, it becomes critical to create robust verification environments that are maintainable and reusable across different versions and configurations of IPs thus reducing the overall development life cycle. This paper describes how Software design patterns can be used for creation of a robust verification environment for a configurable multi-layer protocol. We have tried use these patterns to solve certain problems that we faced during the testbench development for a configurable MIPI DSI IP . Several design patterns are described along with the specific problem that they are used to solve.|
|Speaker:||Pavan Yeluri - Nvidia
|Authors:||Pavan Yeluri - Nvidia
Ranjith Nair - NVIDIA
|7.2||Unified Test Writing Framework for Pre and Post Silicon Verification|
|Day by day there is an increasing need of integrating/reusing the infrastructure across all the stages of product development right from pre-silicon design verification to post-silicon test validation, evaluation and applications board validation. We propose a framework, built on UVM centric digital verification environment that not only enables analog designers/test writers to write tests without having to know the complexities of the underlying UVM but also opens up a common communication medium over which the design, test, evaluation and application can talk and exchange tests/high level functions. This framework is generic and can be used by any project as most of the infrastructure needed is being dumped from IP-XACT by custom generators.|
|Speaker:||Rahulkumar Patel - Analog Devices, Inc.
|Authors:||Rahulkumar Patel - Analog Devices, Inc.
Pablo Cholbi - Analog Devices, Inc.
Sivasubrahmanya Evani - Analog Devices, Inc.
Raman K - Analog Devices, Inc.
|7.3||Towards Early Validation of Firmware Using UVM Simulation Framework|
|This paper would propose a methodology to co-verify a ‘C’ based firmware in UVM based RTL simulation platform thus allowing an early functional readiness for the firmware. It uses the System Verilog DPI (Direct Programming Interface) to interface RTL simulation environment with the ‘C’ based firmware APIs while GCC (GNU Compiler Collection) is used to compile the firmware. The paper would also discuss on several other constructs that the methodology plays a substantial role in; specifically in terms of improving the time to market, ensuring the firmware quality, and creating opportunities for the FPGA and post-si engineers to focus on actual HW issues. The methodology being proposed here is well proven in verifying the firmware well ahead of silicon and even sometimes before emulation commencement, simultaneously ensuring consistency across IP and SoC platforms for HW sequences like boot time configuration, initialization, run time sequences, and complex trainings. This also encapsulates a unique feature of extracting the statement and branch coverage of the ‘C’ based firmware code thus providing a quantification for the extent of APIs validated, in turn projecting the emotional confidence that an engineer may carry to silicon power-on.|
|Speaker:||Amaresh Chellapilla - Intel
|Authors:||Amaresh Chellapilla - Intel
Pandithurai Sangaiyah - Intel