25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
WEDNESDAY September 25, 10:30am - 11:00am | Grand Victoria Ballroom
Panel: Can Designs be Signed Off with Formal Verification Alone?
Ashok Kumar Natarajan - Intel Corp.

Formal verification has improved in leaps and bounds in recent years, in performance, capacity and usability. Once only effective for control-dominated designs with shallow state-space, formal is nowadays being applied to much more complex designs involving data transportation and even data transformation, with increasing complexity and state depth. But are we at the point where complex designs can be signed off with formal alone? At what point is simulation still required?

Takeaways: The panel audience should hear lively debate with useful advice on the following:

  • Realistic limits of formal verification in terms of design size, complexity and style

  • Formal bug hunting techniques to complement simulation

  • Formal verification metrics and sign-off methodology

  • Where simulation is still necessary

  • How UVM-based and formal verification are used together in practice

  • Best practices for combining formal and simulation coverage for metric-driven sign-off

Ramana Venkata Barala - Qualcomm Research
Sudhakar Surendran - Texas Instruments
M. V. A. Kiran Kumar - Intel Corp.
Pete Hardee - Cadence Design Systems, Inc.

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