Formal verification has improved in leaps and bounds in recent years, in performance, capacity and usability. Once only effective for control-dominated designs with shallow state-space, formal is nowadays being applied to much more complex designs involving data transportation and even data transformation, with increasing complexity and state depth. But are we at the point where complex designs can be signed off with formal alone? At what point is simulation still required?
Takeaways: The panel audience should hear lively debate with useful advice on the following:
•Realistic limits of formal verification in terms of design size, complexity and style
•Formal bug hunting techniques to complement simulation
•Formal verification metrics and sign-off methodology
•Where simulation is still necessary
•How UVM-based and formal verification are used together in practice
•Best practices for combining formal and simulation coverage for metric-driven sign-off
Biography: Ashok Kumar Natarajan (Moderator) Ashok currently heads the Intel silicon validation team , focusing on the devices product line . He has 19+ years of overall semiconductor experience in areas of pre-silicon/post-silicon and has managed simulation , emulation , post silicon and formal teams in his prior roles. Ashok was one of the early users of formal technology and pioneered the deployment of formal flows for various IP/SOC’s he has managed . He holds a Master’s degree from University of Tennessee and a Bachelors from College of Engineering , Guindy , Chennai.
Biography:Barala Venkata Ramanamurthy Ramana is Director at Qualcomm, currently leads Qualcomm SOC design verification. Majorly working on Mobile , Compute, Infotainment , and IOT chips. He has about 20years of semiconductor experience in the area of logic design, pre-silicon/post-silicon verification. Ramana has rich experience in development of Test environments be it, System Verilog , Vera , UVM , C based and Portable stimulus. He holds Bachelors in Electronics and communication from Andhra university , Visakhapatnam, Andhra Pradesh.
Biography: Sudhakar Surendran: Sudhakar is a Technical lead and Member, Group Technical Staff at Texas Instruments, currently focusing on verification methodologies. He has earlier worked and led teams on IP verification, SoC verification, mixed-signal verification, emulation, prototyping, and silicon validation. He has more than 20 publications and three patents on verification and micro-architecture
Biography: M. V. A. Kiran Kumar: Kiran is the Principal Engineer for formal verification in Graphics design team, intel. He did his masters at the indian institute of Sciences, Bangalore in 2003 and has been working for intel since then. He started his career as a logic design engineer and explored backend, circuit design, verification before he found his niche in Formal verification. He is the co-author of the book on Formal verification and has one patent and more than 70 publications on FV to his name. He currently leads the formal verification efforts for the graphics designs at intel and drives FV across various IPs and SOCs.
Biography: Pete Hardee: Pete is Product Management Director for the System and Verification Group (SVG) at Cadence Design Systems. He joined Cadence in early 2010 and since 2013, he has been responsible for Cadence’s formal verification product lines, including JasperGold following the Jasper acquisition in 2014. Prior to Cadence, Pete worked in various applications, marketing and sales roles at Synopsys and CoWare. He holds a degree in electrical engineering from Imperial College, London, and an MBA from Warwick Business School, both in the UK.
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