25 - 26 September, 2019

Radisson Blu Bengaluru

Bangalore, India

Event Details

MP Associates, Inc.
THURSDAY September 26, 2:00pm - 3:30pm | Grand Victoria B
Portable Stimulus
Ramana Barala - Qualcomm India Pvt. Ltd.
Accellera’s  emerging Portable Test and Stimulus Standard (PSS) defines a specification to create a single representation of stimulus and test scenarios usable by a variety of users across many levels of integration under different configurations. In this exciting track we will see how various companies adopt PSS which defines high-level verification intent and creates test cases targeting different execution environments, such as simulation, emulation, hardware prototypes, and real silicon. Here we will see some of the limitations of this upcoming standards and how different teams use techniques blended with tool support to overcome these challenges. Overall this session will benefit new users, who are trying to adopt this for legacy SV/UVM/C test framework reuse and give insight in to preserving existing tests and enable portability across blocks to SoC test benches.

8.1Designing A PSS Reuse Strategy
The recently-released Accellera Portable Test and Stimulus Standard (PSS) promises to boost verification reuse by allowing a single description of test intent to be reused across IP block, subsystem, and SoC verification environments, and provides powerful language features to address verification needs across the verification levels and address the specific requirement of verification reuse. However, language features on their own do not guarantee productive reuse of test intent. This paper describes methodology and a planning process to minimize duplicated effort and maximize the reuse benefits of adopting the Accellera Portable Test and Stimulus Standard.
 Speaker: Sagar Karia - Mentor, A Siemens Business
 Authors: Matthew Ballance - Mentor, A Siemens Business
Sagar Karia - Mentor, A Siemens Business
8.2Benefits of PSS Coverage at SOC and its Limitations
With growing adoption of Portable stimulus standard (PSS) for complex SOC Verification, tests scenarios like multi-core, cache-coherent, low power were generated automatically with the help of PSS model/graph-based test generator solutions. Now It’s important to collect the simulation results obtained from these to ensure the auto generated tests scenario’s match our desired verification goals as per Plan which remains an outstanding challenge at SOC level. In this paper we like to share our experiences while migrating our PSS model with functional coverage support and discuss on the importance of PSS Coverage for SOC Testbenches, its challenges & limitations. PSS tools offers two kinds of coverage i.e. Gen-time, Run-time. Gen-time coverage: PSS Generation coverage is defined in cover groups defined under component, actions, tokens. The coverage data is dumped out along with test generation data without the need to run the simulation, this allows user to analyze the quality of stimulus much before actual test run helping the user to generate efficient stimulus. Run-time coverage: Run time coverage is collected from post simulation runs currently unsupported in PSS-DSL. This coverage is intended to cover use case scenario’s like Concurrent traffic, complex traffic sequence, performance scenarios...etc. Benefits of PSS coverage: • With PSS Gen time coverage data obtained during from test generator engines allows to create optimized set of tests based on the specific coverage goals this helps to improve quality of stimulus even before simulation runs. • Able to analyze and avoid if invalid scenario gets generated • Eliminate redundancy in tests • Check the test intent is followed from the action sequence coverage details. • Limitations of gen coverage: • Ability to define coverage goals that span across multiple actions within a scenario is not supported in PSS. • Ability to define coverage goals in terms of temporal relationships between events at runtime is not supported in PSS
 Speaker: Sundararajan Haran - Qualcomm India Pvt. Ltd.
 Authors: Sundararajan Haran - Qualcomm India Pvt. Ltd.
Saleem Khan - Qualcomm India Pvt. Ltd.
8.3A Pragmatic Approach Leveraging Portable Stimulus From Subsystem to SOC Level and SOC Emulation
The growing complexity of SoC’s these and early time to market poses great challenges for verification closure. This paper targets various levels of verification closure from module to SoC. With the motivation to adhere portable stimulus-based approach emphasize developing C based stimulus from beginning and to reduce time to market, this paper demonstrates leveraging C tests and testbench infrastructure from subsystem to SoC to SoC emulation to GLS closure. Considering the requirement of reusability, portability and interoperability the infrastructure is developed around TLM 2.0 Generic Payload for all communication interfaces. This paper demonstrates the advantages of fast simulation as well as SV powerful constraint randomization, UVM sequence layering and ease of use and all this encapsulated in C wrapper used via DPI function calls to reuse at SoC.
 Speaker: Karandeep Singh - NXP Semiconductors
 Authors: Joachim Geishauser - NXP Semiconductors
Karandeep Singh - NXP Semiconductors
Aditya Chopra - NXP Semiconductors
Nitin Verma - NXP Semiconductors