Event Details

MP Associates, Inc.
WEDNESDAY September 25, 09:45 - 10:30 | Grand Victoria Ballroom
Keynote: The Evolution of Static Verification
Keynote Speaker:
Sridhar Seshadri - Synopsys, Inc.
Static verification aims to find RTL bugs efficiently. It has evolved from Lint to CDC and RDC, to cover all aspects of design. As design complexity has increased, so has the number of clocks, resets and power domains. What was once considered a large full-chip five years ago is now an IP; one of 50 blocks in a large SoC.  This keynote looks at the static verification landscape and how it has evolved to support chip complexity, along with the unique challenges and opportunities posed by sophisticated chips for automotive systems, AR/VR platforms, and AI applications with 5G connectivity. Can machine learning help designers be productive and mitigate growing SoC challenges?

Biography: Sridhar Seshadri, Vice President R&D in the Verification Group at Synopsys, is responsible for static verification solutions. He received his bachelor’s degree in computer science from Bangalore University and master’s degree from SUNY Buffalo. Sridhar has over 25 years of EDA experience. Highlights from various roles at Synopsys include lead on VCS simulator team for performance optimizations and driver of SystemVerilog implementation in VCS, delivery of VC Static Platform, VC LP and VC Formal, and management of ZeBu R&D with an emphasis on unique solutions in emulation debug.

Thank you to our Sponsor