DV Tutorial: Making the Most of the UVM Register Layer and Sequences

Within a UVM verification environment, the Register Layer and Sequence classes provide many features to generate the complex stimulus patterns required to test registers within a Design-Under-Test (DUT). Engineers who are new to UVM often fail to take advantage of these features because they are either not aware of their existence (UVM contains many details for beginners to take-in) or they do not properly understand how to use them. This tutorial takes a closer look at the operation of sequences and sequencers; the effective use of run-time phases; the operation of the register layer front-door sequences, back-door sequences and predictors; and will provide a better understanding of how to use these features together in a "joined-up" way, that makes the most of their capabilities for providing high-quality stimulus.

Event ID: 
117a22d5-bbb7-42b5-a8ca-8c7164ce1390
Event Type: 
Tutorial
Location: 
Turret
Event Time: 
Thursday, September 14, 2017 -
16:00 to 17:30
Session Number: 
9
Session Number: 
9
Session Number Suffix: 
T
confID: 
241
Event Sponsor Image URL: 
https://dvcon-india.org/sites/dvcon-india.org/files/images/2017/Doulos-Logo.png