DV Tutorial: Maximizing Productivity and Achieving Formal Verification Closure with Confidence

Rapidly growing design functionality has an explosive impact on verification complexity. Result of this growing complexity, verification teams are looking for innovative technologies that complement and accelerate their flows. The latest advances in formal verification are a powerful driver for this. In this tutorial, we will discuss how to use formal technologies for faster verification flows and the methodology for how to measure and achieve formal verification closure. Industry experts from Synopsys will use real world design scenarios to show how certain verification problems are extremely well suited to be solved with formal verification. These include applications such as Connectivity Checking, Register Validation, and Design Navigator. With these apps, users save significant time, effort and resources across all design types and sizes (including SoC’s). In addition, the tutorial will provide guidance on a methodology for users to define and metrics to provide insight on coverage and provide confidence on formal verification closure and assess the completeness of their formal environment. Applications such as the Formal Testbench Analyzer and Formal Core provide the visibility and confidence needed for functional sign-off.

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Thursday, September 14, 2017 -
16:00 to 17:30
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