DV Tutorial: Recent Trends in AMS Co-Simulation for Low Power Focus and Efficiency Improvement

Ever increasing importance and amount of DMS and AMS co-simulation as an integral part of mixed-signal design and verification cannot be over emphasized. It plays an important role not only in ensuring quality of design and system integration before tape out, but also towards test readiness for silicon test, validation and characterisation including failure debug, root-cause analysis and correlation. AMS design verification has always remained a challenge considering the cost of setup, execution time, debug, and in catching bugs early in the design stage. These factors are owing to tremendous design advancements in recent times, such as low power designs with multiple power domains, especially with on-chip voltage regulators, power switches & isolation. These design advancements mandate the need for much advanced, robust, heterogeneous and comprehensive mixed-signal verification methodologies during both RTL and gate level (GL) AMS co-simulations. Verification engineers primarily rely on IP owners and/or existing information such as power intent (PI) to provide the supply information to the interface elements (IEs) inserted by the tool at analog-digital boundaries. As the verification proceeds, debugging mixed-signal simulation failures also gets difficult because of the complex nature of the designs. It’s becoming unaffordable to wait for hours/days for AMS co-simulations to finish and then start the debug. Debugging in the course of simulation thus becomes paramount and leads a way to interactive mode in AMS co-simulations, just the way it is done in digital design verification (DV). Moreover, AMS designs today are not comprehended just at transistor level or digital, but also with some of the analog part of the design modeled with real numbers. Real number (RN) models are hand-coded to represent the desired quantity (V or I) at desired accuracy. Accordingly, IEs inserted between such real numbers and analog signals should also support voltage or current conversion. Apart from having these features in EDA tools, we also need ease of creation of AMS setup to effectively use those features. This can be well achieved through GUI based flows. We would need to take care of some corner cases such as, but not limited to, handling purely digital constructs in AMS co-simulations, handling errors arising out of accessing analog signals in digital constructs.

Event ID: 
62d4f098-28d6-40a0-a7f1-1d0f684695cc
Event Type: 
Tutorial
Location: 
Sitara
Event Time: 
Thursday, September 14, 2017 -
16:00 to 17:30
Session Number: 
10
Session Number: 
10
Session Number Suffix: 
T
confID: 
241
Event Sponsor Image URL: 
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