Wrap up a great day of sessions by networking with fellow conference attendees while enjoying a buffet dinner. In addition there will be an update from Accellera and an exciting talk by an invited speaker from Intel Corp.
This tutorial introduces various methodologies employed by design community in managing design and verification complexity using hierarchical static verification techniques. The tutorial covers various aspects of hierarchical verification methodologies discussing advantages, disadvantages and various trade off to be considered in employing these methodologies for static verification signoff. A number of verification flows including top and block level flows and various combinations of flows are presented.
The CCI working group has been active for a number of years, and has now some major announcements. CCI is critical for interoperability, both between models and different tool environments, between different model foundries, and within models themselves. The working group has taken a holistic approach to finding mechanisms that can be used to ease the pain of interoperability.
By all measures, UVM is the most successful verification standard ever created in the EDA community. And that’s no boast. From inception to today, it has swept through project teams worldwide. It is now an IEEE Standard. The tutorial will focus on those changes and how you can prepare for the IEEE standard today. As we review those changes, we will also examine the impact it will have on your existing verification environments including how to debug and regold those environments improving your ability to share verification IP among globalized teams.
Rapidly growing design functionality has an explosive impact on verification complexity. Result of this growing complexity, verification teams are looking for innovative technologies that complement and accelerate their flows. The latest advances in formal verification are a powerful driver for this. In this tutorial, we will discuss how to use formal technologies for faster verification flows and the methodology for how to measure and achieve formal verification closure.
IP verification is too-often mistakenly tagged as a solved problem. The reality is that IP verification is plagued with a wide variation in effectiveness – the ability to confirm that new IP fulfils function, is of high quality, and is bug-free; and efficiency – the ability to assure IP quality in reasonable project timescales, and to be able to repeat easily when the IP is reconfigured for use in derivative designs. All of this is exacerbated by the fact that today, we’re dealing with IPs and subsystems as big as yesterday’s chips, and tomorrow’s IPs will be as big as today’s chips.
Much of the history of electronic design automation (EDA) has involved replacement of manual effort by automated processes. Place-and-route tools replaced hand layout, logic synthesis supplanted gate-level netlists, and constrained-random testbenches reduced or eliminated hand-written test vectors. Standardized formats used as input to the automation tools include SystemVerilog, Property Specification Language (PSL), and the Universal Verification Methodology (UVM).