DVCon India 2014 Proceedings

DVCon India 2014 Proceedings

Below are presentations, papers, and posters from DVCon India 2014. Keynote speeches, invited talks, and tutorials are not available for download. You may download individual items below or download all items at once.

Jump to: DV Papers | ESL Papers | Poster Sessions

DV Papers

D2M2.1-DV: Emulation, HW Acceleration, Prototyping

Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based Testbenches Venkateswara Rao Narla, Ranjith Kumar Kotikalapudi, Vikas Verma and Gautam Kumar (Avago Tech) Slides Paper
Low Power Emulation for Power Intensive Designs Harpreet Kaur, Piyush Kumar Gupta, Mohit Jain and Jitendra Aggarwal (ST) Slides
MDLL and Slave Delay Line performance analysis using novel delay modeling Avinash Shambu, Abhijith Kashyap and Kalpesh Shah (Texas) Slides Paper

D2M2.2-DV: UVM

Responding to TAT Improvement Challenge through Testbench Configurability and Re-use Akhila M, Kartik Jain and Mukesh Bhartiya (Intel) Slides Paper
Global Broadcast with UVM Custom Phasing Jeremy Ridgeway and Dolly Mehta (Avago Tech) Slides Paper
Configuration in UVM: The Missing Manual Mark Glasser (Nvidia) Slides Paper

D2M2.3-DV: Selected Topics

A Framework for Verification of Program Control Unit of VLIW Processors Sharangdhar Honwadkar and Santhosh Billava (Saankhya) Slides Paper
An Automated Systematic CDC Verification Methodology based on SDC setup Sulabh Kumar Khare and Ashish Hari (Mentor) Slides Paper
Simulation Based Pre-Silicon Characterization Venkatseema Das, Saurabh Pandey, Arif Mohammed and Nishant Gurunath (Texas Instruments) Slides Paper

D2A1.1-DV: ABV Formal, CDC, X-Check

Choice is Yours: Either Struggle to Tame "X" in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL Park Nitin Kumar Jaiswal, Harsh Garg and Mayank Digvijay Bindal (Freescale) Slides Paper
Model Extraction for Designs Based on Switches for Formal Verification Naman Jain and Amar Patel (Mentor) Slides Paper
Usecase VCD (ValueChangeDump) Based Power Signoff Methodology for the Automotive SoC Raghavendra Dattatraya, Poornima Prahlada, Manikandan Panchapakesan Slides

D2A1.2-DV: UVM, IP-To-SOC Reuse

Bring IP Verification Closure to SoC, Scalable Methods to Bridge the Gap between IP and SoC Verification Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Vipin Verma and Sachin Jain (Freescale) Slides Paper
Reusable UVM_REG Backdoor Automation Balasubramanian G, Bob Blais and Allan Peeters (PMC-Sierra) Slides Paper
UVM Usage for Selective Dynamic re-Configuration of Complex Designs Kunal Panchal and Pushkar Naik Slides Paper

D2A1.3-DV: Selected Topics

Compliance and Requirements-driven Development Methodology for Realizing System on Chip Based Solutions Based on ISO26262 Functional Safety Standard for Road Vehicle Haridas Vilakathara (NXP) Slides Paper
Efficient Methods for Analog Mixed Signal Verification: Interface Handling Methods, Trade-offs and Guidelines Lakshmanan Balasubramanian, Bharath Kumar Poluri, Shoeb Siddiqui and Vijay Kumar Sankaran (Texas, IITM,Candence) Slides Paper
Expediting Verification of Critical SoC Components using Formal Methods Maddipatla Shankar Naidu, Lakshman Easwaran and Nuni Srikanth (Ericcson & Mentor) Slides Paper

D2A2.1-DV: UVM

Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces Amlan Chakrabarti and Malathi Chikkanna (AMD) Slides Paper
UVM, VMM and Native SV: Enabling Full Random Verification at System Level Ashok Chandran (Analog Devices) Slides Paper
Cross-Domain Datapath Validation Using Formal Proof Accelerators Aarti Gupta, Bindumadhava S S, Achutha Kiran Kumar M V, Jun B Liu (Intel) Slides

D2A2.2-DV: Low Power, CDC

Retention Based Low Power DV Challenges in DDR Systems Subhash Joshi, Sangaiyah Pandithurai and Siddesh Halavarthi Math Revana (Qualcomm) Slides Paper
Low Power Verification Challenges and Coverage Recipe to sign-off Power Aware Verification Deepmala Sachan, Thameem Syed S, Venugopal Jennarapu and Raghavendra Prakash (Intel) Slides Paper
Power Aware CDC Analysis at RTL for Faster Design Verification Closure Anindya Chakraborty, Naman Jain, Saumitra Goel (Mentor) Slides Paper

D2A2.3-DV: AMS

Automated Correct-by-Construct Methodology for RTL Design and Analog Mixed-signal Test Bench Generation Enables Early Design Closure of Mixed-signal SoC Lakshmanan Balasubramanian, Murugesh Prashanth Subramaniam, Atul Ramakant Lele and Ranjit Kumar Dash (Texas Instruments) Slides Paper
Functional Verification of CSI2 Rx-PHY using AMS Co-simulations Ratheesh Mekkadan (AMD) Slides Paper
SERDES Rx CDR Verification using Jitter, Spread-spectrum Clocking (SSC) Stimulus Somasunder Sreenath, Raghuram Kolipaka, Chirag Shah and Parag Lonkar (Cadence) Slides Paper
 

ESL Papers

D2A1.1-ESL

Runtime Fault-Injection Tool for Executable SystemC Models Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker and Thomas Kruse (Infineon) Slides Paper
Virtual Hardware Setup for Automotive Software Testing Karthikeyan Ramachnadran (Robert Bosch) Slides
Rapid Virtual Prototype Model Development using UML and IP-XACT Deepak Kurapati, Aravinda Thimmapuram (Intel) Slides Paper

D2A1.2-ESL

RTL Quality for TLM Models Preeti Sharma (Synopsys) Slides Paper
Trace Based Simulation Infrastructure For DDR Controller Evaluation Abhilash Nair, Amit Nene, Ritesh Sojitra, Prashant Karandikar and Prajakta Bhutada (Texas Instruments) Slides Paper
Utilizing SystemC/TLM for adapting block level verification environment for reuse at System Level and Embedded Environments Wasiq Zia (Cadence) Slides Paper

D2A2.1-ESL

Design Methodology for Highly Cycle Accurate SystemC Models with Better Performance Simranjit Singh and Sameer Deshpande (Infineon) Slides Paper
Data Flow Based Memory IP Creation Infrastructure Abhilash Nair, Praveen Buddireddy, Rashmi Venkatesh, Tor Jeremiassen and Prajakta Bhutada (Texas Instruments) Slides Paper
 

Posters Sessions

DV Posters

How to Reuse Sequences with UVM ML-Open Architecture Hannes Froehlich (Cadence) Poster Paper
A New Epoch is Beginning: Are You Getting Ready to Step into UVM1.2? Roman Wang, Uwe Simm Poster Paper
Performance Verification of a 6Gbps HSLink Receiver Including Equalization and Clock Data Recovery using Mixed Signal Simulations Aashish Bhide, Abhishek Chowdhary, Alok Kaushik, Vivek Uppal Poster Paper Slides
Mixed-level Verification Methodology for Power-up Verification of eSRAMs Prakhar Raj Gupta, Deepak Singhal, Rakesh Shenoy Panemangalore, Kshitij Verma Poster
Gate-level Simulations - Continuing Value in Functional Simulations Ashok Chandran and Roy Vincent Poster Paper
Pre-Silicon Debug Automation using Signature Extraction and Data-mining Kamalesh Vikramasimhan, Senthilkumar Narayanaswamy, Kaustubh Godbole, Deepak Sadasivam Poster Paper
Please! Can Someone Make UVM Easy to Use? Raghu Ardeishar and Rich Edelman (Mentor) Slides Paper

ESL Posters

High Level Modelling Of Physical Layer Noise Parameters Using SystemC Prem Kumar Lohani, Ranjani K, Ravi Shankar R, Sundaresan C, Chaitanya Cvs (Whizchip & Manipal Edu) Poster
Performance Estimation of Multi-Processors Systems with Hybrid Approach Smei Habib Poster