DV Tutorial: Low-Power Methodology for Making Micro-Architectural and Sequential Changes at RTL to Achieve Predictable Power Savings Throughout the Design Flow

With the rapid explosion in number of hand-held devices, power has become overriding concern to stay competitive and at the same time be able to meet ever increasing demand for more and more features. Traditionally, task of reducing power has been left to implementation tools which deploy various gate-level techniques (sizing, area-recovery, Vth mixing, pin-swapping etc.) to reduce design power. However, in past few years, there has been growing realization that implementation tools can provide very limited power savings and to maximize the returns, design changes need to be made at RTL and above. A recent survey has shown that 80% of design power is decided by decisions taken at RTL and above stages. However, task of power saving is not as simple as asking RTL designers to write power-aware RTL. There are hundreds of techniques (each for registers, clock, datapath, memories etc.) which can be applied at RTL to save power. Applying each technique for every design object and estimating the power saving can be a very prohibitive task, with serious impact on the design schedule, and is the single biggest reason why RTL designers shy away from doing aggressive power optimizations at RTL. This tutorial will provide an insight into RTL power saving techniques (micro-architectural as well as sequential with examples) which work well in practice. We will cover methodologies which can help RTL designers in qualifying right power-saving techniques applicable for his/her design and associated power improvement. Focus will be on those techniques which are known to provide power savings at every stage in the design flow (till post-layout).

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Thursday, September 14, 2017 -
14:00 to 15:30
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