DV Tutorial: Optimizing IP Verification – Which Engine?

IP verification is too-often mistakenly tagged as a solved problem. The reality is that IP verification is plagued with a wide variation in effectiveness – the ability to confirm that new IP fulfils function, is of high quality, and is bug-free; and efficiency – the ability to assure IP quality in reasonable project timescales, and to be able to repeat easily when the IP is reconfigured for use in derivative designs. All of this is exacerbated by the fact that today, we’re dealing with IPs and subsystems as big as yesterday’s chips, and tomorrow’s IPs will be as big as today’s chips. In short, the barrier to realizing true IP reuse is verification, not design. This tutorial shares best practices and gives real actionable guidelines for how and where to apply UVM-based dynamic and formal verification engines, within a common metric-driven framework, to optimize IP verification efficiency and effectiveness. Choosing the Appropriate Engine We can optimize verification by knowing which IP blocks are best verified with formal and which are best done using UVM; based on design type, sequential depth and interface type to reduce the number of dynamic verification cycles needed. We offer practical guidelines for choosing the appropriate engine, and best practices for verification reuse based on that method. We also highlight verification IPs that can be used by multiple engines to streamline verification of common interface protocols. Further guidelines are given for optimizing dynamic and formal regressions, maximizing compute-farm resources, and applying innovative bug-hunting techniques to attain greater confidence that IP is bug-free.

What you will learn:
• Best practices for rigorous reusable UVM-based dynamic verification for IPs
• Practical methodologies to select and fully verify IPs with formal verification
• New planning and management optimizations to improve farm utilization
• How to apply formal and simulation coverage results in a coherent metric-driven verification flow

Who should attend:
• IP Developers
• Verification engineers/leads responsible for IP, Block, and Subsystem level verification
• Verification managers and design managers responsible for delivering quality IPs and SOCs on time

Event ID: 
a17adf0a-b99a-4539-9a7d-537362d0aa38
Event Type: 
Tutorial
Location: 
Grand Ballroom
Event Time: 
Thursday, September 14, 2017 -
14:00 to 15:30
Session Number: 
3
Session Number: 
3
Session Number Suffix: 
T
confID: 
241
Event Sponsor Image URL: 
https://dvcon-india.org/sites/dvcon-europe.org/files/images/2016/Cadence_WEB.png