DV Tutorial: Various Facets of Hierarchical Static Verification

This tutorial introduces various methodologies employed by design community in managing design and verification complexity using hierarchical static verification techniques. The tutorial covers various aspects of hierarchical verification methodologies discussing advantages, disadvantages and various trade off to be considered in employing these methodologies for static verification signoff. A number of verification flows including top and block level flows and various combinations of flows are presented. Expert Users will also present their case studies and learnings as a part of the presentation.

--Speakers marked with (*) will be unable to attend--

Event ID: 
95678967-eabc-40c5-9dc9-f419b2332af2
Event Type: 
Tutorial
Location: 
Royal Ballroom
Event Time: 
Thursday, September 14, 2017 -
14:00 to 15:30
Session Number: 
1
Session Number: 
1
Session Number Suffix: 
T
confID: 
241
Event Sponsor Image URL: 
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