Enjoy networking with other DVCon India attendees while visiting the many interesting exhibitors located throughout the conference hallways.
Ever increasing importance and amount of DMS and AMS co-simulation as an integral part of mixed-signal design and verification cannot be over emphasized. It plays an important role not only in ensuring quality of design and system integration before tape out, but also towards test readiness for silicon test, validation and characterisation including failure debug, root-cause analysis and correlation. AMS design verification has always remained a challenge considering the cost of setup, execution time, debug, and in catching bugs early in the design stage.
Within a UVM verification environment, the Register Layer and Sequence classes provide many features to generate the complex stimulus patterns required to test registers within a Design-Under-Test (DUT). Engineers who are new to UVM often fail to take advantage of these features because they are either not aware of their existence (UVM contains many details for beginners to take-in) or they do not properly understand how to use them.
Automated formal apps have introduced a new generation of D&V engineers to the power of formal verification without the pain. This success has inspired renewed interest in creating formal testbenches for DUT-specific verification challenges that are well suited to formal. In this tutorial – focused on engineers who are completely new to formal verification -- you will learn how to:
Enjoy a tea break while you mingle with DVCon India's exhibitors, located in hallways throughout the conference area.
With the rapid explosion in number of hand-held devices, power has become overriding concern to stay competitive and at the same time be able to meet ever increasing demand for more and more features. Traditionally, task of reducing power has been left to implementation tools which deploy various gate-level techniques (sizing, area-recovery, Vth mixing, pin-swapping etc.) to reduce design power.
Consistent, high performance unleashed by every generation of NVIDIA’s Graphics Processing Units (GPUs) makes them invaluable to systems ranging from supercomputers to gaming rigs to self-driving cars. Validating GPU performance with high accuracy and confidence is key to delivering high performance GPUs for the above systems. Over the years, though GPUs’ complexity has grown manifold, NVIDIA engineers have finessed the art of validating GPU performance and ensuring that performance goals are met, long before production-ready chips tape out.
Take time to network and mingle with other conference attendees while
enjoying a buffet lunch. Exhibits will be open throughout the conference
area, so be sure to stop by the booths and see what's new.
Thirty-year old hardware emulation is enjoying a renaissance of sorts as it finds itself at the foundation of most SoC verification flows. Many reasons account for the tool's turn of luck, moving it out of dusty backrooms and into a new starring role. Its popularity is a result of numerous factors, ranging from improvements in functionality and usability to design complexity and more embedded software for each design to easier-to-use platforms.