DVCON INDIA 2026 – “Architecture to Analysis”
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The theme for this year conference is “Architecture to Analysis” where the community focus is towards the usage of specialized design, verification languages and latest trends in System and IP level modelling, Virtual Prototyping & ESL, Architecture and Design, RISC-V and its ecosystem, 3DIC Multi-Die designs, and Post Silicon Validation.
DVCon is seeking tutorial topics that are current, have a high-level of interest and offer strong continuing educational content.
Tutorial sponsors reach a captive audience during the 90 min of educational sessions and have the opportunity to follow-up with them during breaks, at the exhibits, and following the event.
DVCon is a highly targeted venue for engineers addressing major design and verification issues. You can position your company at the forefront of these discussions by sponsoring either of the Tutorials listed below. Submit proposals by June 30th, 2026. For suggested topics and timeline, see below.
SPONSORED TUTORIAL: 3,50,000 /-
Sponsorship Includes:
- 90 min technical presentation
- Copy of the Sponsored Tutorial Attendee List (email addresses included)
- Tutorial content will be publicized via monthly newsletters, DVCon website, Conference Program and in the Opening Session presentation slides
- Other promotional items like banners, flyers, gift items, etc. can be distributed at the event.
- Presenters for the tutorial are entitled to a complimentary one-day registration
- 3 complimentary one-day registrations for the tutorial presentation
Sponsored tutorials will be reviewed and approved by the program committee with respect to technical depth and applicability. In case of multiple organizations presenting a sponsored tutorial only the organizing company would get the sponsorship benefits mentioned above.
Detailed guidelines for preparing the presentations will be made available after selections are final.
TUTORIAL PROPOSAL REQUIREMENTS
Deadline: June 30th, 2026
DVCon tutorials are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the tutorial.
- Attendee expectations are high regarding currency of topic, depth of engineering content and breadth of real- life examples
- The Tutorial Chair will review final presentation materials to ensure high quality educational content
- Include suggested presenter’s names, affiliations & biographies.
- Your proposal should be a short abstract of the tutorial, two to five paragraphs, 1,000 words maximum
- Presentation slides need to be supplied in an electronic format in advance of the conference. Presentation slides will be distributed to the attendees in electronic format. Hard copies will not be provided
- Please indicate if this tutorial is a “hands-on” session or lecture format
- Any necessary additional hardware that you may require must be provided by the tutorial organizers
SUGGESTED TOPICS (but not limited to)
DVCon tutorials are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the tutorial.
Topic Area 1: Languages and Methodologies
- SystemVerilog for Verification and/or Design
- SystemC /C/C++ Design and/or Verification of systems.
- Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
- Verification Productivity Methods (e.g., PY-UVM)
- Clock and Reset Domain crossing.
- Portable Stimulus
Topic Area 2: System and IP level modelling, Virtual Prototyping & ESL
- Architectural analysis/performance modeling
- Mixed-signal modeling and verification
- Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT), IP Protection
- Digital Twins
- Embedded software verification
Topic Area 3: Hardware/Software & Pre/Post-silicon validation
- Emulation
- Hardware/Software Co-development
- FPGA Prototyping, FPGA & UVM use models
- Debug for design and verification
- Post SI Debug
Topic Area 4: Automotive and Embedded Systems
- Functional Safety
- Security
Topic Area 5: Formal and Static
- Formal Methodology and Static Analysis
Topic Area 6: AI assisted Design Flows
- AI assisted Design and Verification
- Debug AI Assistant
Topic Area 7: Analog and Mixed Signal verification
- Verilog/Systemverilog/UVM– AMS
- Analog and Mixed Signal verification trends
Topic Area 8: Design & Verification Trends
- 3D-IC & Multi-Die DV challenges
- Machine Learning applications for verification and design
- Open-source hardware/software/architecture (e.g., RISC-V)
- SoC and Software-driven Verification
- High-level Synthesis
- Coverage-driven Verification
- Low-power Design and Verification techniques
- Secure/Encrypted IP-based SoC design methods
IMPORTANT DEADLINES
- June 30, 2026: Proposals due. Submit at given link below
- July 8, 2026: Accept/Reject notification.
- July 15, 2026: All Tutorial content due for Conference Program and website: tutorial title, abstract, speaker names, affiliations and biographies
- August 1, 2026: Draft Presentation slides due to DVCon Tutorial Chair – Given Link below.
- August 8, 2026: Presentation feedback due to presenters on slides
- August 15, 2026: Final slides due for final production for attendee distribution
CONFERENCE SCHEDULE
September 1, 2026 — Keynote, Workshops, and Tutorials
September 2-3, 2026 — Keynotes, Technical Sessions, and Panel Discussions
Tutorial Chair
Sundararajan Ananthakrishnan
Cadence
sundara@cadence.com
Tutorial Co-Chair
Ray Ranjan Varghese
Synopsys
ray.varghese@synopsys.com