Call for Papers deadline is extended to August 31, 2021.
September 6-7, 2022
Call for Tutorials
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C, C++, PERL, Tcl, and Python. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design techniques, IP based SoC design methods, reference flows and AMS/DMS design and portable stimulus.
DVCon is looking for tutorial topics that are current, have a high-level of interest and offer strong continuing educational content.
Tutorial sponsors reached a captive audience during the half-day educational sessions and had the opportunity to follow-up with them during breaks, at the exhibits, and following the event.
DVCon is a highly targeted venue for engineers addressing major design and verification issues. You can position your company at the forefront of these discussions by sponsoring either of the Tutorials listed below. Submit proposals by August 15th, 2021.
TUTORIAL PROPOSAL REQUIREMENTS
DVCon tutorials are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the tutorial.
Attendee expectations are high regarding currency of topic, depth of engineering content and breadth of real-life examples. The Tutorial Chair will review final presentation materials to ensure high quality educational content Include suggested presenters’ names, affiliations, and biographies.
Your proposal should be a short abstract of the tutorial, two to five paragraphs, 1,000 words maximum. Presentation slides need to be supplied in an electronic format in advance of the conference. Presentation slides will be distributed to the attendees in electronic format. Hard copies will not be provided. Please indicate if this tutorial is a “hands-on” session or lecture format. Any necessary additional hardware that you may require must be provided by the tutorial organizers.
SystemVerilog for Verification and/or Design
SystemC /C/C++ Design and/or Verification of systems.
SoC and Software-driven Verification
Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
High-level modeling and Synthesis challenges and Verification.
Low-power Design and Verification techniques
Secure/Encrypted IP-based SoC design methods
Debug for design and verification
Mixed-signal modeling and verification
Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT)
Embedded software verification
Verification Productivity Methods
Formal Methodology and Static Analysis
Left-shift with Emulation and/or Prototyping technologies.
Post SI Debug
Moving from proprietary solutions to standards-based design and verification
Applying Machine Learning (ML) techniques to address the verification challenges
PROPOSAL SUBMISSION PROCESS
Proposals should be 2-3 pages in length and should contain:
The topic and the Title, Detail about the problem statement and proposed solution/flow.
The issues to be discussed, including a short listing of pro and con arguments
Short biographies of the moderator and prospective panelists
Conference Sponsored By: Accellera Systems Initiative is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process. Accellera.org