Invite for Global Design Contest

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.

This invite for the design contest, titled “VEGA microprocessor (RISC-V) based Design & Verification Challenge” presents unique opportunities for academic students:

1. Achieve deeper understanding of RISC-V architecture, indigenous VEGA Microprocessor and ecosystem.
2. Explore the design and verification space for better performance.
3. Implement your own hardware accelerator on industry standard FPGA in for a specified application.
4. Opportunities to interact with experts from industry and academia.
5. To win cash prizes and potential intern opportunities at leading-edge VLSI and sponsor companies

VEGA is a series of high-performance processors including India’s first indigenous 64-bit multicore RISC-V based Superscalar Out-of-order Processor, developed by C-DAC as part of the Digital India RISC-V (DIR-V) program by the Ministry of Electronics and Information Technology (MeitY), Govt. of India. These high-performance processors are based on the open-source RISCV Instruction Set Architecture with Multilevel caches, Memory Management Unit and Coherent Interconnect. Six processors are currently available in the VEGA processor family. These indigenous microprocessors employing the state-of-the-art architecture have a performance which is at par with other commercially available processors. The microprocessors are available as soft IPs and are amenable/ customizable for better performance/power targeted for various strategic/industrial/commercial applications.

The design contest will involve:

• Problem statement solution based on RTL Design, Functional verification, and implementation on an FPGA.
• Each team with maximum of 3 members should register and will be given five months with specific milestones for completion in multiple stages.
• There will be mentoring sessions at different milestones during the contest duration.
• Remote access to Genesys 2 FPGA Board and simulator/synthesizer will be provided.
• Final implementation, demonstration and evaluation on Genesys board at the venue.

Congratulations to Design Contest Stage 2A winners!