The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.
In addition to the specific topic areas suggested below, submissions may incorporate:
Usage of Electronic Design Automation (EDA) tools such as Simulation, Emulation, Formal verification, Virtual prototyping and/or FPGA prototyping
Usage of specialized design and verification languages such as System Verilog, SystemC assertions in SVA or PSL
General purpose and scripting languages such as C, C++, Perl, Python, Tcl usage
Accellera Portable Stimulus Standard applications
Applications of design patterns or other innovative language techniques
AMS languages user case scenario
Internet of Things applications
This call for abstracts solicits for papers and corresponding presentations that are highly technical and reflect real-life experiences and emerging trends in various domains. Submissions are encouraged in (but not restricted to) the following areas:
VERIFICATION AND VALIDATION
Advanced methodologies and testbenches
Verification processes, Regressions and Resource management
Debug and analysis of complex designs
Multi-language design and verification
Hardware/Software co-design and co-verification of embedded systems
DESIGN AND VERIFICATION REUSE AND AUTOMATION
Bridging verification and validation across multiple engines
SoC and IP integration methods and tools
Applications of the Accellera Portable Stimulus Standard
Configuration management of IP and abstraction levels
Methods and flows for functional safety standard compliance (e.g., ISO 26262, DO-254)
Safety and security in design, verification and validation
Requirements-Driven Verification Methodologies
IP protection and security
New methods and tools supporting functional safety and security
MIXED-SIGNAL & LOW-POWER DESIGN & VERIFICATION
AMS modeling for concept and system-level design
Application of mixed-signal extensions in verification (e.g., UVM-MS)
Real-number modeling approaches
Self-checking testbenches in analog verification
Low-power design and verification (e.g., UPF)
STATIC & FORMAL VERIFICATION
Clock Domain Crossing design and verification
Formal Verification techniques and methodology
Applications of Static and Formal techniques
ESL & VIRTUAL PROTOTYPING
High-level synthesis from ESL languages
Usage of higher level of abstraction, SystemC modelling etc.
Virtual Prototyping and Digital Twins
SYSTEM LEVEL & SOFTWARE DESIGN
Transaction-level modelling (e.g., System-C TLM)
Software for verification
Software development and verification
PAPER SUBMISSION PROCESS
Note: New Submission Guidelines for DVCon India 2021. Template available in Resources.
An initial submission is required before the full paper. The submission should be between a minimum of 600 words and a maximum of 1200 words (approximately 2 pages, not including diagrams, figures or tables).
In general, please provide enough details so that the Technical Program Committee can evaluate the potential quality and interest of your proposed presentation at DVCon India.
The initial submission should include:
Title: The paper title.
Contact information: Name, affiliation, phone number and email address for all authors.
Short Abstract: Outline that clearly states the context and motivation of your contribution, approx. 100 words.
Related Work: Identify other work on which this submission will be built, and the novelty of the paper.
Application: Clearly describe the technical contribution, reflect real life experiences, and its industrial application.
(Preliminary) results: Summarize the results. State how these differ from previous work or state-of-the-art on the same subject.
Conclusions: Summarize major conclusions and findings presented in the paper.
Accepted authors will be invited and agree to do the following:
Submit the final version of the paper (max. 8 pages) after incorporating feedback from the TPC
One Author must Register for the conference
Submit a copyright form
All accepted authors agree to present an oral or poster presentation at the conference (15th, 16th Dec 2021).
Please note: Consistent with the requirements for other DVCon India presentations, your presentation may contain your company logo only on the title slide, and should use the provided templates.
Please do your initial submission via the EasyChair – Submit Here by August 7, 2021. The website will open on June 09, 2021.
June 09, 2021: Website Open for Submissions – EasyChair – Submit Here August 7, 2021: Deadline for initial submission September 15, 2021: Accept/reject notification sent to all authors October 15, 2021: Full paper due for review by TPC November 15, 2021: Final paper due December 15 – 16, 2021: Conference.
December 15, 2021 — Tutorials and Panels
December 16, 2021 — Technical paper sessions, poster session
DVCon India honours the Best Paper/Presentation and Best Poster submissions. The awards will be selected by the attendees at DVCon India based on the quality of both the paper and the presentation.