Call for Workshops
Call for Workshops
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well as general purpose languages such as C, C++, Python, PERL and Tcl. Tools and methodologies include the use of machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP-based SoC design methods, reference flows and AMS design and verification.
DVCon is seeking workshop topics that are current, have a high-level of interest and offer strong continuing educational content. Workshop sponsors reach a captive audience during the 45min of educational sessions and have the opportunity to follow-up with them during breaks, at the exhibits, and following the event.
DVCon is a highly targeted venue for engineers addressing major design and verification issues. You can position your company at the forefront of these discussions by sponsoring either of the Workshops listed below. Submit proposals by June 30th 2023. For suggested topics and timeline, see below.
DVCON SPONSORED WORKSHOP: 1,75,000/-
Sponsorship Includes:
- 45 min technical presentation
- Copy of the Sponsored Workshop Attendee List (email addresses included)
- Workshop content will be publicized via monthly newsletters, DVCon website, Conference Program and in the Opening Session presentation slides
- Other promotional items like banners, flyers, gift items, etc. can be distributed at the event.
- Presenters for the workshop are entitled to a complimentary one-day registration
- 3 complimentary one-day registrations for the workshop presentation
Sponsored workshops will be reviewed and approved by the program committee with respect to technical depth and applicability. In case of multiple organizations presenting a sponsored workshop only the organizing company would get the sponsorship benefits mentioned above.
WORKSHOP PROPOSAL REQUIREMENTS
Deadline: June 30th, 2023
DVCon workshops are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the workshop.
- Attendee expectations are high regarding currency of topic, depth of engineering content and breadth of real- life examples
- The Workshop Chair will review final presentation materials to
ensure high quality educational content - Include suggested presenters names, affiliations & biographies
- Your proposal should be a short abstract of the workshop, two to five paragraphs, 1,000 words maximum
- Presentation slides need to be supplied in an electronic format in advance of the conference. Presentation slides will be distributed to the attendees in electronic format. Hard copies will not be provided
- Please note that this workshop session will not include any “hands-on” activity.
- Any necessary additional hardware that you may require must be provided by the workshop organizers
SUGGESTED TOPICS
DVCon workshops are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the workshop.
Languages and Methodologies
- SystemVerilog for Verification and/or Design
- SystemC /C/C++ Design and/or Verification of systems.
- Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
- Verification Productivity Methods (e.g., PY-UVM)
- Clock and Reset Domain crossing.
- Portable Stimulus
Modeling & Prototyping
- Mixed-signal modeling and verification
- Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT), IP Protection
- Digital Twins
- Embedded software verification
Hardware/Software & pre-silicon validation
- Emulation
- Hardware/Software Co-development
- FPGA Prototyping, FPGA & UVM use models
Automotive and Embedded Systems
- Functional Safety
- Security
Formal and Static
- Formal Methodology and Static Analysis
Design and Verification trends
- SoC and Software-driven Verification
- High-level Synthesis
- Coverage-driven Verification
- Low-power Design and Verification techniques
- Secure/Encrypted IP-based SoC design methods
- Moving from proprietary solutions to standards-based design and verification
- Application-specific design verification challenges and techniques
- Machine Learning applications for verification and design
- Open-source hardware/software/architecture (e.g., RISC-V)
- 3D-IC & Multi-Die DV challenges
- Debug for design and verification
- Post SI Debug
WORKSHOP DEADLINES
- June 30th, 2023: Proposals due. Submit at given link below
- July 8th, 2023: Accept/Reject notification
- July 15th, 2023: All Workshop content due for Conference Program and website: workshop title, abstract, speaker names, affiliations and biographies
- August 1st, 2023: Draft Presentation slides due to DVCon Workshop Chair – Given Lin below
- August 12th 2023: Presentation feedback due to presenters on slides
- August 19th 2023: Final slides due for final production for attendee distribution
CONFERENCE SCHEDULE
September 13, 2023 — Keynotes, Accellera Day tutorial, Workshops, and Tutorials
September 14, 2023 — Keynotes, Technical Sessions, and Panel Discussions
Submission via EasyChair – Submit Here
Conference Sponsored By: Accellera Systems Initiative is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process. Accellera.org
Tutorial Chair
Lokesh Babu Pundreeka
Cadence Design Systems, Inc.
lokeshp@cadence.com
Tutorial Co-Chair
Narashimha Babu
Synopsys
Narasimhababu.GVL@synopsys.com