Call for Workshops

DVCon workshops are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the workshop.

Topic Area 1: Languages and Methodologies

• SystemVerilog for Verification and/or Design
• SystemC /C/C++ Design and/or Verification of systems.
• Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
• Verification Productivity Methods (e.g., PY-UVM)
• Clock and Reset Domain crossing.
• Portable Stimulus

Topic Area 2: System and IP level modelling, Virtual Prototyping & ESL

• Architectural analysis/performance modeling
• Mixed-signal modeling and verification
• Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT), IP Protection
• Digital Twins
• Embedded software verification

Topic Area 3: Hardware/Software & Pre/Post-silicon validation

• Emulation
• Hardware/Software Co-development
• FPGA Prototyping, FPGA & UVM use models
• Debug for design and verification
• Post SI Debug

Topic Area 4: Automotive and Embedded Systems

• Functional Safety
• Security

Topic Area 5: Formal and Static

• Formal Methodology and Static Analysis

Topic Area 6: AI assisted Design Process

• AI assisted Design and Verification
• Debug AI Assistant

Topic Area 7: Analog and Mixed Signal verification

• Verilog/Systemverilog/UVM– AMS
• Analog and Mixed Signal verification trends

Topic Area 8: Design & Verification Trends

• 3D-IC & Multi-Die DV challenges
• Open-source hardware/software/architecture (e.g., RISC-V)
• SoC and Software-driven Verification
• High-level Synthesis
• Coverage-driven Verification
• Low-power Design and Verification techniques
• Secure/Encrypted IP-based SoC design methods