Call for Panels
DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and Specman, as well as general purpose languages such as C and C++, PERL, Tcl and Python. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS design.
Conference attendees are primarily designers of electronic systems, ASICs, and FPGAs, as well as those involved in the research, development, and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature and reflect real life experiences in using these languages and tools.
Deadline: May 30th, 2023
Proposals to be submitted online via EasyChair – SUBMIT HERE
DVCon is planning to host two highly focused panel discussions. DVCon is looking for panels that are lively, controversial, and provoke discussion on a specific topic of interest to the community. Panel sessions should not consist of paper presentations but should have plenty of discussion engaging the audience. Panels are scheduled for 1 hour each on Sep 13th & Sep 14th, 2022. Please make sure that moderator and panelists are available on schedule day.
DVCon will attempt to work with the original organizer in refining the panel, but if this is not successful, another organizer may be appointed. If multiple panel suggestions are submitted with similar topics, the committee may choose to accept one over the others, to merge the proposed panels, or to reject all of them.
We invite you to contribute your knowledge and experience within the hardware design and verification, advanced tools, and new methodologies areas, and to participate in the valuable exchange of ideas. Panels should combine experiences in each area with forward-looking statements regarding technology and industry trends, and challenges likely to be encountered as the state of the art continues to progress.
- Closing DV Gaps in ever increasing SOC Design size Vs shrinking Time to Market
- DV Methods/flows which enabling vertical reuse (IP->SS->SOC) and horizontal reuse (simulation->emulation->prototyping)
- Application of Machine Learning /AI to optimize the verification efforts
- Dealing with the technical and logistical challenges of multi-site projects
- Designing and/or verifying complex ASICs and FPGAs using multiple HDLs and/or HVLs in a design cycle
- Experiences adopting functional-safety related standards such as ISO26262, DO-254 etc.
- Dealing with Mixed-signal challenges in the contest of Complex SOC’s
- RISC-V adoption for India and Rest of the world
- India Driving Global Verification Bandwagon
- Challenges in Design and Validation of Chiplets and its integration
- Can Formal technologies alone be sufficient to close Verification
- May 30th, 2023: Proposal Deadline
- June 30th, 2023: Accept/Reject notification
- July 31st, 2023: Final panel title, abstract and panelists names due for website
- Proposals should be 2-3 pages in length and should contain:
- The title, if possible, formulated as a thought-provoking question
- The topics to be discussed, including a short listing of pro and con arguments
- Short biographies of the moderator and prospective panelists
- Any special requirements
Conference Sponsored By: Accellera Systems Initiative, which is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process. Accellera.org
Analog Devices India