DVCon 2024

September 18-19

Conference Registration

IMPORTANT DEADLINES

AUG 5, 2024

Final paper Submission for TPC/Shepard Review

AUG 9, 2024

Early Bird Registration Ends

AUG 26, 2024

Speaker Confirmation, Presentation & Copyright Forms Due

SEPT 8, 2024

Design Contest Stage 2B Submission Date

SEPT 18-19, 2024

DVCon India 2024 Begins

WELCOME MESSAGE BY GENERAL CHAIR

On behalf of the DVCon India 2024 steering committee, it is my pleasure to welcome you all to the 9th edition of the Design and Verification Conference in India planned from 18- 19th September 2024 in Bangalore, India. The theme of this year’s conference is “Architecture to Analytics – A2A“.

We want to carry forward the momentum, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2024. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days and will have an…

VISION TALK

Empowering Innovation: Harnessing Collective Wisdom across Tools, Processes, and People!

Harry Foster

Chief Scientist Verification

Siemens DISW

KEYNOTES

The Increasing Verification Horizon in the Era of Pervasive Intelligence

Vikas Gautam

VP Engineering

Synopsys

Subrangshu Das

Director

Google Silicon

Accelerated Infrastructure in an AI World

Puneet Agarwal

VP & CTO, Data Center Switching

Marvell

AI for Verification – Today’s Reality Vs. Tomorrow’s Promise

Matt Graham

Product Management Group Director

Cadence

The Future is Formal

Ashish Darbari

Founder & CEO

Axiomise

Navigating the Future of Chip Design Verification in an Era of Rapid Semiconductor Innovation

Apurva Kumar

Director – Semiconductor Vertical

Quest Global

DVCON INDIA 2023 AWARD WINNERS

Thanks For a Great 2023 Conference!

Special thanks to all our attendees, speakers, exhibitors, sponsors, and everyone who made DVCon India 2023 a success!

Lifetime Achievement Award

Nilesh M Desai, ISRO

Notable Contribution – Individual

Achutha Kiran Kumar V M, Intel

Notable Contribution – Individual

Somasunder Kattepura Sreenath, Samsung

Best Academic Institution

RV College of Engineering, Bangalore

General Category

Best Paper

Python Empowered GLS Bringup Vehicle
Debarati Banerjee, Nikhil Singla, Shantha B, Pandithurian Sangaiyah
Google

Best Paper Runner-Up

Breaking Down Barriers: Achieving seamless protocol conversion with UVM component layering
Santosh Mahale, Shantanu Lele
Marvell

Formal & Static

Best Paper

PropGen: An automated flow to generate SVA properties for formal and simulation methods
Amith Shambhu, Vishal Dalal, Basavaraj Naik
Infineon

Best Paper Runner-Up

When Last Minute Formal Verification Strikes Gold: A Case Study on Finding Starvations and Deadlocks in a Project nearning Tape-in using RTL embedded assertions
Abhishek Potdar, Sachin Kumawat, Sudhanshu Srivastava, Anshul Jain
Intel

Best Poster

Best Poster Winner

Design verification of a cascaded mmWave FMCW Radar
Shweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharvanan and Kavya P S
NXP Semiconductors

Best Poster Runner-Up

Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations
Sudhanshu Srivastava, Aman Vyas, Sachin Kumawat, Rupali Tewari
Intel

Notable Mentions

Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV
Ravindrareddy Pulicharla, Nitin Neralkar, Chayan Pathak, Venkatesh Chepuri, Madhusudhan Koothapaakkam, Sourabh Bhattacharjee and Piyush Upadhyay
Qualcomm

Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design
Pravat Kishor Nayak, Vikrant Kapila, Pushpa Naik and Niketkumar Sharma
Intel