Call for Papers deadline is extended to August 31, 2021.
DECEMBER 14-16, 2021
WELCOME MESSAGE BY GENERAL CHAIR
On behalf of the DVCon India 2021 steering committee, it is my pleasure to welcome you all to the 6th edition of the Design and Verification Conference in India planned from 14-16th Dec 2021 as a virtual conference. We are bringing DVCon India 2021 in a wholistic virtual platform comprising of in-depth technical content for 3 days. This is an upward shift and progression from the Accellera Day that we organized in 2020. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey.
The IC industry continues to grow thanks to the Systems, Automotive and Technology unicorns venturing to design their own chips and well-established IC companies and start-ups bringing in new innovations and chip architectures. While there are a lot of new designs and architectures, we continue to evolve in…
Anil Kempanna, Vice President, IOTG, leads Silicon Engineering for HSPE. In less than 3years, Anil has built a strong 1200 member silicon engineering team that delivered 15+ SOCs with multiple innovations (Hetero Core, Foveros, Ultra-low power). As part of driving the Corporate HVDM transformation, Anil has been instrumental in surfacing problem statements and driving solutions across teams World-Wide for 5+ programs which has significantly reduced Time-To-Market. Anil is extremely passionate about grooming young leaders and fostering a culture of Quality, Predictability and Vibrancy across the teams he leads.
Anil has 25+ years of experience in the semiconductor industry in US, Europe and Asia. During his career, Anil has delivered over 40+ products in multiple market segments like Smartphones, Modems, IoT, Networking and Small Cell devices. Prior to joining Intel, Anil has worked in Qualcomm, Texas Instruments, Cadence and at a fixed Broadband wireless startup, Ensemble Communications.
Anil holds a Master’s degree in Science and Electrical Engineering from Wright State University and a Master’s degree in Business Administration from University of Phoenix.
Sundarrajan Subramanian is Senior Director, Engineering at Qualcomm Bangalore and is responsible for managing the SoC Front-End organization for India HW. The SoC Front-End functions include Design, Design Verification (DV), Design-For-Test (DFT) and Security, Power management, Debug cores development. The SoC Front-End teams in India (Bangalore, Noida and Hyderabad) are responsible to deliver end to end products spanning multiple technology nodes and varied markets across Mobile, IoT, Automotive, XR etc.
Sundar’s previous responsibilities at Qualcomm include leading the SoC development and productization for Qualcomm thin modems across multiple generations. He has held positions previously at Teradyne (USA), Cisco Systems (USA), Texas Instruments ( India) in the areas of Design-For-Test (DFT), Implementation, Post Si debug, Design Management . Sundar has been in the VLSI industry for more than 23 years and has a Master’s degree in Solid State Electronics from Arizona State University, USA.
Ashok Chandran is an ADI Fellow and Design Verification Director. He sets technology direction & methodology for verification across multiple Wireless Communication SoCs from Analog Devices. He led deployment of advanced verification methodologies, piloting emulation and virtual prototyping for some of the most complex mixed signal SoCs at ADI. His expertise spans across circuits, software, communications systems and application of right tools and methodologies to enable high performance system verification.
Earlier, as part of Automotive group, he led system level verification on multiple Blackfin DSP SoC projects and driving adoption of VMM, UVM and Formal methodologies for Analog Devices. In 2021, he was promoted to an ADI fellow for his vision, leadership, and championing of system verification within ADI.
Christopher Tice is vice president of Hardware Marketing and Manufacturing in the Verification Group, responsible for driving the growth of Synopsys’ verification business based on a foundation of systems tools and solutions addressing fast-growing verticals such as automotive, AI, networking, and 5G. He is also responsible for Synopsys Hardware Manufacturing
Before joining Synopsys, he was an entrepreneur-in- residence at SK Telecom Innopartners. Mr. Tice spent 16 years at Cadence Design Systems where he was senior vice president and general manager of the Hardware and Systems Groups. Prior roles included vice president of Quickturn Design Systems and general manager of Weitek’s Processor Business Group.
Mr. Tice received his BSEE with honors from the University of Florida and attended the MBA School at Florida Atlantic University. He was elected as an inaugural member of the Electrical and Computer Engineering Academy of the University of Florida in 2009.
JOIN US AT DVCON INDIA 2021
DVCON INDIA 2021
The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.
DVCON INDIA 2019
Thanks For a Great 2019 Conference!
Special thanks to all our attendees, speakers, exhibitors, sponsors, and everyone who made DVCon India 2019 a success!
Best Paper & Poster Winners
10.2 Automatic Generation of Infineon Microcontroller Product Configurations