Call for Papers deadline is extended to August 31, 2021.
September 18-19, 2024
Radisson Blu, Marathahalli, Bangalore
MAY 7, 2023
Deadline for Extended Abstract Submission
MAY 30, 2023
Deadline for Call for Panels
June 1, 2023
Design Contest Stage 1 Deadline
JUNE 30, 2023
Deadline for Call for Tutorials/Workshops
SEPTEMBER 18-19, 2024
DVCon India 2024 Begins
WELCOME MESSAGE BY GENERAL CHAIR
On behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference. We want to carry forward the momentum, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2023. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey.
This year’s edition will have a good blend of Vision and Keynote talks, lively panel discussions tutorials and technical sessions spread across both the days. We are looking at some of the feedback and see how to set an agenda that provides…
Breaking Down Barriers: Achieving seamless protocol conversion with UVM component layering
Santosh Mahale, Shantanu Lele Marvell
Formal & Static
PropGen: An automated flow to generate SVA properties for formal and simulation methods
Amith Shambhu, Vishal Dalal, Basavaraj Naik Infineon
Best Paper Runner-Up
When Last Minute Formal Verification Strikes Gold: A Case Study on Finding Starvations and Deadlocks in a Project nearning Tape-in using RTL embedded assertions
Abhishek Potdar, Sachin Kumawat, Sudhanshu Srivastava, Anshul Jain Intel
Best Poster Winner
Design verification of a cascaded mmWave FMCW Radar
Shweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharvanan and Kavya P S NXP Semiconductors
Best Poster Runner-Up
Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations
Sudhanshu Srivastava, Aman Vyas, Sachin Kumawat, Rupali Tewari Intel
Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV
Ravindrareddy Pulicharla, Nitin Neralkar, Chayan Pathak, Venkatesh Chepuri, Madhusudhan Koothapaakkam, Sourabh Bhattacharjee and Piyush Upadhyay Qualcomm
Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design
Pravat Kishor Nayak, Vikrant Kapila, Pushpa Naik and Niketkumar Sharma Intel
Nikhitha Avula, Vinay Ratnala and Tarun Gupta Indian Institute of Technology, Hyderabad
1st Runner up
Thishakya Bandara, Janindu Leelananda and Tharaka Kodithuwakku University of Moratuwa, Sri Lanka
2nd Runner up
Akshata D Rokhade, Amogh P Guddimath and K Venkat Anish SDM College of Engineering and Technology, Dharwad
Unleashing AI/ML for Faster Verification Closure
Design verification is one of the most expensive and tedious activities undertaken in electronic system development. Advances in machine learning (ML) algorithms, software and practices in the last few years have given verification engineers a powerful suite of tools to attack this problem. Verification tool builders have leveraged these ML advances to accelerate coverage closure, generate better simulation distributions, and improve core verification algorithms. We will explore how exploiting supervised, unsupervised and reinforcement learning have enabled order of magnitude gains in closure convergence and verification cycle reduction.
We are now in the world of Smart Everything from voice assistants, advanced robotics, drone-based delivery to autonomous cars and chatbots. This begs the question, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. When we consider where time is spent in verification, coverage convergence and debug consume 70% of overall verification time. In addition to time spent, misinterpretation of specifications is a major source of bugs. With the rapid evolution of AI/ML technologies, how can we automate some or many of these activities? What technologies are available today and what is on the horizon? With the advent of LLM (large language) and GPT (generative pre-trained transformer) models, what are the possibilities in design verification? Just like there are 6 levels of driving automation, from driver assistance to conditional automation to full automation, what level is the current state of verification? This keynote address will explore these topics and look ahead to the future of autonomous verification.
Speaker: Sandeep Mehrotra Title: Vice President of Engineering Company: Synopsys
Smart Verification: Faster is not enough!
Buckle up, fellow tech explorers! The ever-changing landscape of semiconductor design is calling for a cosmic paradigm shift in how we conquer upcoming verification challenges. Sure, we’ve zoomed towards faster and more efficient verification methodologies thanks to tech wizardry, but we can’t warp past the fact that sheer speed alone won’t guarantee us complete solutions. As we reach for new frontiers, the complexity of design and verification tasks skyrockets, beaming us towards an urgent need to harness the power of intelligence.
Get ready for a keynote that takes you on a thrilling journey, exploring the vital role of smarter solutions in the design and verification process. It’s not just about speed, fellow adventurers! We’ll boldly discuss the factors that highlight the limitations of solely relying on speed, all while shining a spotlight on the pressing demand for intelligent EDA solutions. Brace yourselves for a universe of possibilities, where performance optimization and tackling intricate design and verification challenges go hand in hand with intelligent solutions.
Practical applications of machine learning in design verification
ML (Machine Learning) is transforming the way we work in a wide range of industries and this has been accelerated by generative AI (Artificial Intelligence) applications such as ChatGPT. In this presentation we investigate how ML and AI can potentially be applied in DV (Design Verification), from automation of requirements/specification analysis and test plan generation, through test bench creation and test generation, to debug and coverage closure.
There is a very wide range of ML techniques available and this presentation first surveys those techniques and how they have been applied (successfully and unsuccessfully) to DV in both academia and in real projects. The objective is to better understand how to apply the most promising techniques to a wide range of DV activities to ultimately make DV both more efficient and effective.
The main objective of the presentation is to give the audience a better understanding of what is achievable of applying ML in DV and to give practical suggestions on their adoption.
Overview of the various ML techniques
Better understanding of the potential applicability of ML to DV
Practical advice and experience of applying ML to DV
Journeying Beyond AI: Unleashing the Art of Verification
The semiconductor industry is undergoing a transformative shift, embracing novel design methodologies and innovative flows to meet the demands of a rapidly evolving technological landscape. In this keynote address, we will explore how these advancements, such as AI-driven Electronic Design Automation (EDA), System of Chips (SoCs) utilizing Chiplets with UCIe, and cutting- edge 2.5D & 3D advanced packaging techniques, are revolutionizing chip production. This transformative journey positions the semiconductor industry to emerge as a trillion-dollar market by 2030, fueled by the creation of complex chips boasting trillions of transistors.
The rise of disruptive technologies, such as AI, Cloud computing, and Autonomous Vehicles, has sparked a pressing need for sophisticated SoCs and chips specially designed to cater to these domains. These intricate designs incorporate standard CPUs, GPUs, FPGAs, and specialized AI accelerators, providing the foundation for groundbreaking innovation. With AI serving as a key driver for progress, its pervasive influence is permeating every industry sector.
Within the realm of EDA, Machine Learning has emerged as a vital tool, significantly enhancing the efficiency of the design and verification processes. Leveraging the power of Machine Learning, we are propelled towards the adoption of AI-driven EDA, facilitating the creation of advanced chips that fuel the growth and proliferation of emerging technologies. During this keynote, we will delve into the uncharted territory of verification challenges stemming from these new designs. Furthermore, we will illustrate how AI-driven EDA empowers verification engineers to efficiently validate these state-of-the-art chips, enabling them to unleash their creative potential and innovate with unprecedented freedom.
Speaker: P R Sivakumar Title: Founder & CEO Company: Maven Silicon
AI for Chip Design: Scaling DV Capacity to Meet Massive Demand Growth
According to analysts, the electronic industry’s annual revenue is estimated to double by 2030, reaching one trillion USD. Chip design is at the heart of this growth, but costs are rapidly increasing, and the number of chip design projects is expected to increase fourfold in the next decade. Despite this growth, the industry must address productivity gaps and a talent pool shortage, which has become a significant challenge for the chip design industry worldwide. AI and Generative AI are crucial in boosting design and verification productivity by orders of magnitude. It enables many domains in the chip design and implementation cycles, including functional, safety, security verification and logic optimization at various design abstractions, starting from architectural levels down to implementation for software and hardware models. Despite the impressive industrial advancements and successful applications of AI technologies for various software domains, the application for the chip design domain is still very young, considering its high expected impact on the industry. This talk aims to inspire and inform the DV community to accelerate research, development and deployment of AI and Generative AI solutions through discussion and description of some of the areas of research and development Cadence has undertaken with it’s key partners.
Speaker: Dr. Ziyad Hanna Title: Corporate Vice President & R&D GM Israel Company: Cadence Design Systems
Bugs, Transistors, Chips, and Waves – A Panoramic View of the Journey from Four to a Quintillion, and Beyond
Semiconductors – this technological marvel, deeply etched into our lives, stands not only as a beacon of human achievement, but also as the cornerstone of our digital age. Join us as we dive into a world where bugs, transistors, and waves coalesce in a remarkable narrative that defines the semiconductor and computing landscape. Embark on a thrilling odyssey through time, back to the humble origins of the semiconductor industry. Meet the trailblazing pioneers who broke barriers. Amaze at the evolution of technology, from the earliest transistors to the architectural wonders of today’s chips, sculpting our digital landscape and the world as we know it. Our voyage doesn’t stop at the present. Together, we’ll peer into the crystal ball to glimpse the horizon of possibilities. From the silent switching of transistors to the propagation of waves – the future is just a semiconductor away! So, brace yourself for an enlightening expedition that traverses the timeline, from the era of bugs to the epoch of quintillions. The future of semiconductors and computing is as exciting as its past – and you’re about to see why!
Enabling highest quality Pre & Post Silicon Verification and Validation Strategies for SoC
This Keynote from Srinivasa Kumar, VP – Engineering QCT, aims to cover the verification and validation strategies that enables complex SoCs. As the SoC landscape continues to evolve with ever-increasing complexity and rapidly shrinking product development timelines, the need to have smarter validation methodologies from Pre-Silicon to Post-Silicon, leading all the way up to Commercialization is briefly touched upon. The keynote covers certain unique methodologies such as big box emulation, concurrency scenario, power and performance aware scenarios, to clock scaled emulation builds in the Pre-silicon phases of SoC Design, and also briefs on the Silicon bring up of CPUs, DDR, Peripherals, Multimedia blocks, and the low power mode use cases, Performance and power correlation, “Defective Parts Per Million” (DPPM) strategies, that enables faster time to market in the post-si phase. With the event of customer bring up happening before Engineering Sample release parallelly with Post-Si execution, and the resultant accelerated customer launches, this key note touches upon the compelling need to compress “time to market schedules” through our volume validation, System Level Test debug strategies, and how the validation team remains a bridge between HW and SW organization enabling “on time” and “quality commercialization” of our complex SoCs to ensure high quality product.
Verification: A Critical Enabler for the $Trillion Chip Design Industry
The semiconductor industry is projected to hit $1T in revenue in five years’ time. We will outline the main growth drivers fueling this growth and the resultant areas of exploding complexity that must be managed to achieve the growth. Meeting this challenge requires huge increases in verification throughput that can only be met with verification flows utilizing smart management of multiple different software and hardware verification engines. Machine learning will be a critical technology, for both management and engine-level, to enable meeting the verification challenge.
Speaker: Lokesh Babu Pundreeka Title: AE Director – System Verification Group Company: Cadence Design System
Verification Challenges in Rapidly Evolving Ecosystem
5G is revolutionizing the digital world by introducing radically new use cases across a spectrum of industries. These use cases pose a unique challenge to Design and DV community in coming up with highly optimized, scalable, and interoperable solution. The talk goes over these challenges and dwells on possible solutions.
Speaker: Joy Chandra Title: Sr. Director Engineering Company: Qualcomm