Call for Papers deadline is extended to August 31, 2021.
September 13-14, 2023
SEPTEMBER 13-14, 2023
DVCon India 2023 Begins
WELCOME MESSAGE BY GENERAL CHAIR
On behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and Verification Conference in India planned from 13- 14th September 2023 as an In-Person conference. We want to carry forward the momentum, excitement and the enthusiasm witnessed during last year’s edition into DVCon India 2023. The conference would be following the contemporary Indian version of a two-day conference with in-depth technical content spreading across both the days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey.
This year’s edition will have a good blend of Vision and Keynote talks, lively panel discussions tutorials and technical sessions spread across both the days. We are looking at some of the feedback and see how to set an agenda that provides…
Special thanks to all our attendees, speakers, exhibitors, sponsors, and everyone who made DVCon India 2022 a success!
A Generic Configurable Error Injection Agent for On-Chip Memories
Niharika Sachdeva, Arjun Suresh Kumar, Anil Deshpande, Somasunder Kattepura Sreenath, Raviteja Gopagiri and Damandeep Saini Samsung
Best Paper Runner-Up
Disciplined post silicon validation using ML intelligence
Amaresh Chellapilla and Pandithurai Sangaiyah Intel
The Formal way – Fast and Accurate Hashing Algorithm Verification
Sini Balakrishnan, Sireesha Tulluri, Bindumadhava Ss and Disha Puri Intel
Best Paper Runner-Up
OIL check of PCIe with Formal Verification
Vedprakash Mishra, Carlston Lim, Anshul Jain, Zhi Feng Lee, Jian Zhong Wang and Achutha Kirankumar V M Intel
Best Poster Winner
A novel approach to reduce power consumption by bridging the gap between standalone functional scenario and real time scenario at SoC
Harshal Kothari, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan and Somasunder Kattepura Sreenath Samsung
Best Poster Runner-Up
Reset Verification using Formal tool
Arju Khatun and Shiva Nagendar Pokala Qualcomm
Notable Mentions (General Category)
Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components
Praneeth Uddagiri, Veera Satya Sai Gavirni and Prashantkumar Ravindra Analog Devices
An Efficient Methodology for Development of Cryptographic Engines
Sandesh Kanchodu, Tarun Rajendra Mittal, Sachin Kashyap and Subramanian Parameswaran Samsung
Nikhitha Avula, Vinay Ratnala and Tarun Gupta Indian Institute of Technology, Hyderabad
Hackathon – 1st Runner up
Priyanshu Gautam, Pritam Das and C Sanmukh Siva Sai Indian Institute of Technology Kharagpur
Hackathon – 2nd Runner up
Tushar Upadhyay, Yellur Vishal Rao and Ayush Kumar Manipal Institute of Technology
Unleashing AI/ML for Faster Verification Closure
Design verification is one of the most expensive and tedious activities undertaken in electronic system development. Advances in machine learning (ML) algorithms, software and practices in the last few years have given verification engineers a powerful suite of tools to attack this problem. Verification tool builders have leveraged these ML advances to accelerate coverage closure, generate better simulation distributions, and improve core verification algorithms. We will explore how exploiting supervised, unsupervised and reinforcement learning have enabled order of magnitude gains in closure convergence and verification cycle reduction.
Subi Kengeri joined Applied in March 2020 to start a new initiative, AI Systems Solutions. His team is chartered with the goal of architecting differentiated AI Systems leveraging Applied’s fundamental innovations.
Prior to joining Applied, Subi was the CTO and vice president of world-wide client solutions at Globalfoundries, responsible for enabling differentiated SoC and systems solutions. Subi joined Globalfoundries in 2009 as the vice president of global design solutions responsible for world-wide design engineering and semiconductor eco-system development. He was responsible for determining technology feasibility, competitiveness, and manufacturability of technology platform through cross- functional collaboration of customers, R&D and eco-system. In the role of vice president of CMOS Platforms Business Unit, Subi was responsible for business results.
Subi started his SoC design engineering career at Texas Instruments in 1991 and prior to joining Globalfoundries, he was the senior director of design-technology platform and head of North America Design center, at TSMC. Subi has been granted 47 U.S. design engineering patents and has given over 100 invited talks and press interviews.
Speaker: Subramani (Subi) Kengeri Title: Vice President, AI Systems Solutions Company: Applied Materials
Emerging Design/Verification Technologies and Standards — Which comes first?
Some technologies emerge from a standard, other standards emerge from existing technologies. Our industry is in a constant struggle between innovation and stability. Standardization efforts need to strike a balance between these two driving factors. We will look at the timelines for some current standards to see which came first. Then look at a few emerging technologies to what comes next.
Speaker: Dave Rich Title: Verification Architect Company: Siemens EDA
Verification Challenges, Trends and their Practical Adoption – An ASIC Manager’s Perspective
Multiple surveys suggest that verification continues to take a larger percentage of ASIC pre-silicon development effort and time (typically 60 – 70%) and companies continue to adopt newer methodologies and technologies to increase productivity, quality and time-to-market. However, there are barriers to adoption of such technologies. From the perspective of an engineering manager, new verification techniques should reduce effort and budget whilst improving project schedule, productivity and design quality to help ensure first-pass silicon success. However, it is not always clear which techniques will achieve these for their specific products and development flows and once selected how they can be seamlessly incorporated into existing flows where their benefits can be realised and, ideally, measured. This talk will look at a range of verification techniques and improvements and provide suggestions on how they can be assessed, selected and adopted to make a positive contribution to key project metrics.
Verification: A Critical Enabler for the $Trillion Chip Design Industry
The semiconductor industry is projected to hit $1T in revenue in five years’ time. We will outline the main growth drivers fueling this growth and the resultant areas of exploding complexity that must be managed to achieve the growth. Meeting this challenge requires huge increases in verification throughput that can only be met with verification flows utilizing smart management of multiple different software and hardware verification engines. Machine learning will be a critical technology, for both management and engine-level, to enable meeting the verification challenge.
Speaker: Lokesh Babu Pundreeka Title: AE Director – System Verification Group Company: Cadence Design System
Verification Challenges in Rapidly Evolving Ecosystem
5G is revolutionizing the digital world by introducing radically new use cases across a spectrum of industries. These use cases pose a unique challenge to Design and DV community in coming up with highly optimized, scalable, and interoperable solution. The talk goes over these challenges and dwells on possible solutions.
Speaker: Joy Chandra Title: Sr. Director Engineering Company: Qualcomm