Physical Intelligence Needs a New Engineering Stack: Rethinking Architecture and Execution for Intelligent Physical Systems

As AI moves from generating information to interacting with the physical world, semiconductor development faces a new level of complexity. Delivering intelligent physical systems requires the convergence of architecture, hardware, software, AI models, verification, and execution into a unified engineering workflow. This talk explores how the industry must evolve from traditional chip-centric development to an integrated, AI-accelerated engineering stack that enables faster innovation, higher system reliability, and scalable deployment of Physical Intelligence solutions. The session will share perspectives on the future of semiconductor development and the organizational transformations required to build the next generation of intelligent systems.

Presenter: Anil Kempanna

Title: VP, Global Head of Digital Hardware Design, ADI

Agentic AI for Chip Design: Evolving from Coding Assistants to Super Agents

There is no question that AI has already had significant impact on front end design and verification. However, AI solutions, and impact, are still in their infancy. Unlocking the full productivity potential of AI requires up-leveling solutions and leveraging agentic orchestration, multi-agent, EDA harness for iterative workflows and tight integration with fundamental tools and engines. This presentation will explore the potential, proposed architectures, and challenges of building and deploying Super Agents for chip design and validation.

Presenter: Ziyad Hanna

Title: Corporate VP, R&D, Cadence Design Systems

Ziyad Hanna is a distinguished global technology executive, computer scientist, and AI leader, with more than 35 years of experience shaping the fields of electronic design automation and artificial intelligence. As a Corporate Vice President of Cadence Design Systems, and R&D General Manager, leading the company’s technology innovations and global business with focus on software and AI technologies for the worldwide chip design industry. In 2025, Ziyad Hanna was appointed to lead Cadence’s global artificial intelligence strategy, a role that underscores the company’s deep trust in his visionary leadership and technical excellence. As the strategic head of AI at Cadence, Ziyad is responsible for shaping and executing the company’s direction in artificial intelligence—driving innovation across global teams, identifying transformative opportunities, and steering technological advancement in one of the most critical areas of the future chip design ecosystem. His leadership in this role is pivotal to Cadence’s evolution as a front- runner in AI-driven design and verification technologies. Prior to Cadence, he was the Sr. Vice President, Chief Scientist and General Manager of Jasper the first startup company that made its way to exit and managed by an Arab Israeli General Manager. While being a US permanent resident and leading the company from the Silicon Valley, Jasper earned the Red Herring Top 100 North America award in 2013 and was acquired by Cadence in June 2014. Prior to joining Jasper, Ziyad was Senior Principal Engineer and Group Leader in the Design and Technology division at Intel Haifa. He played a key role in developing computer aided design (CAD) systems that were deployed across nearly all Intel microprocessor designs since the early 1990s. A senior IEEE member and a lecturer in the EECS department at the Technion Israel, Ziyad is very active in the Hi-Tech field and has participated in many international conferences and workshops. He has published more than 30 articles, earned 25 patents, and gave hundreds of talks, a frequent keynote speaker, and respected advisor in various fields in computer science and chaired conferences including the annual Jasper User Group (JUG) for 15 consecutive years. Ziyad received numerous awards including Intel's highest achievement award twice, and Cadence move-the-needle award. He obtained his bachelor’s and master’s degree from Tel Aviv University, and PhD in computer science from Oxford University in England, where he serves as a visiting professor in the computer science department. Ziyad is very active to foster the Hi-Tech in the Arab community. Ziyad was ranked number 39 in The-Marker’s 100 most influential people on the Israel life for year 2019, top the list in the Hi-Tech category. Also, received honorable doctorate from Rubin collage, and his name was included in the list of the most influential people in Hi-Tech by both The-Marker and People and Computers magazines.

Power. Performance. Proofs: Scaling Formal for the AI-Driven Compute Revolution

AI is driving an explosive rise in custom compute, demanding architectures that balance performance, power efficiency, and security. While hyperscalers rely mostly on proprietary, GPU-centric designs, open-source RISC-V offers a flexible alternative-especially for Edge AI. Achieving optimal performance-per-watt means smarter design: tuning microarchitecture, NoCs, floating-point precision, and storage with HBMs and caches. In this talk, we present a breakthrough approach from Axiomise to scalable formal verification, combining abstraction-based methods with custom tool automation. Our solution addresses the full spectrum of challenges in verifying custom silicon, including PPA trade-offs and complex floating-point logic. Using mathematical proofs, we detect deep bugs, deadlocks, and livelocks-delivering formal at scale for the AI era.

Presenter: Hitesh Garg

Title: Vice President and India Managing Director of NXP Semiconductors

Hitesh Garg is the Vice President and India Managing Director for NXP Semiconductors, leading the company’s India operations across Bengaluru, Noida, Hyderabad, and Pune. He plays a key role in strengthening India’s position as a strategic global R&D hub, with a focus on engineering excellence, talent development, and strong alignment with NXP’s global technology and business priorities.

In addition to his India MD responsibilities, Hitesh serves as the R&D Leader for Design Enablement at NXP. In this role, he drives common design platforms, methodologies, reusable IP, and scalable engineering flows that enable product teams across the company to deliver highquality, secure, and reliable silicon with improved productivity and faster timetomarket. His leadership spans multiple technical domains, enabling strong collaboration across diverse engineering teams and geographies.

With over 25 years of experience in the semiconductor industry, Hitesh brings deep expertise across Analog/Mixed Signal design, IP development, product engineering, and largescale R&D leadership. Before joining NXP, he held technical and leadership roles at Conexant Systems, Microchip Technology, and Semiconductor Complex Limited (SCL), contributing to the development of complex products and building highperformance engineering teams. Hitesh holds a Bachelor’s degree in Electronics and Communication Engineering and a Post Graduate Degree in Management from IIM Bangalore. He is recognized for his peoplecentric leadership style and for championing India’s growing role in driving innovation and engineering scale within NXP’s global ecosystem.

Generative AI: Is it Real or Merely a Hallucination?

Generative AI is reshaping the landscape of design and verification, but separating genuine breakthroughs from hype remains a challenge. As artificial intelligence becomes increasingly embedded in our daily workflows—from voice assistants to autonomous systems—the question arises: is generative AI delivering real, practical value in chip design verification, or are we chasing illusions? And, with the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification?

This session will examine the current state of generative AI in design and verification. We’ll explore where Synopsys is investing in agentic solutions and what technology is being implemented in production environments by end users, delivering significant productivity boosts and automation. Join us to discover whether generative AI is truly revolutionizing the industry—or if it’s still more hallucination than reality.

Presenter: Pallab Dasgupta

Title: Vice President of R&D Engineering, Synopsys

Pallab has over 25 years of experience in EDA software development and management in the areas of simulation based functional verification and debug. He is currently responsible for R&D for Synopsys’ industry- leading verification debug product Verdi.