Industry Panels
Industry Panel: Closing DV Gaps in ever increasing SOC Design size Vs shrinking Time to Market
Date: 9/13/2023
Time: 10:30 – 11:30
As the size of System-on-Chip (SOC) designs continues to increase, the time available for Design Verification (DV) is shrinking rapidly. This presents a major challenge for designers and verification engineers alike. The pressure to meet ever-shorter time-to-market (TTM) windows has become a top priority, but it cannot come at the cost of quality. In this panel, we will discuss the best practices for closing the DV gaps that arise from this tension. Our panelists will share their experiences in managing large-scale multi-site projects, sustainable engineering solutions, and successful multi-site projects in India. We will explore the latest trends in DV methodologies, automation, and tools to help close these gaps and ensure high-quality designs. We will also discuss the role of collaboration, communication, and leadership in overcoming these challenges. Join us for an insightful and informative discussion on how to close DV gaps in SOC design and meet the demands of today’s fast-paced marketplace.
Industry Panel: Revolutionizing System-Level Verification and Validation: Implications for India’s Innovation Drive
Date: 9/14/2023
Time: 10:15 – 11:15
The Indian government’s plan to transform a nation of service providers to a nation of research, locally designed products, and premium innovation is taking shape. Many growing market segments show great promise as starting points for this transformation. Particularly automotive and communications. These two market segments are experiencing significant change and the implication on new methodologies and tools is significant. In this panel we will look at what opportunities exist for transformation in semiconductor and system-level verification and validation technologies. As well as explore how existing IP and services companies can expand their business models in innovative ways to support redefining the way things are done. Shakeel Jeeawoody, Siemens, will moderate a panel of system-level design and verification experts, all of whom are assessing efficient and innovative way to deploy tools, IP, and methodologies to meet the requirements of complex system development. Audience participation will be encouraged.
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