Keynotes
The Increasing Verification Horizon in the Era of Pervasive Intelligence
Artificial Intelligence (AI) is driving the transformation of the systems and semiconductor architectures, raising the stakes for verification. The horizon for verification expands beyond the traditional functional verification to include a wide range of metrics to support AI on the edge or in datacenters, from training to inferencing all the way to generative AI.
This keynote presentation will explore why achieving the target metrics needs to start at the architectural stage, especially for multi-die designs. Vikas Gautam (Synopsys) and Ashok Kumar Natarajan (Google) will discuss how to best utilize hardware-assisted verification solutions crunching complex AI workloads to achieve optimal performance and power metrics. They will also provide their perspectives on how built-in debug is a critical component of silicon lifecycle from pre-silicon to in-field deployment. The session will wrap up with their insights on implementing security as an essential expansion of the verification horizon for any state-of-the-art system.
Speaker: Vikas Gautam
Title: VP Engineering
Company: Synopsys
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Speaker: Ashok Kumar Natarajan
Title: Director
Company: Google Silicon
Smart Verification: Faster is not enough!
Buckle up, fellow tech explorers! The ever-changing landscape of semiconductor design is calling for a cosmic paradigm shift in how we conquer upcoming verification challenges. Sure, we’ve zoomed towards faster and more efficient verification methodologies thanks to tech wizardry, but we can’t warp past the fact that sheer speed alone won’t guarantee us complete solutions. As we reach for new frontiers, the complexity of design and verification tasks skyrockets, beaming us towards an urgent need to harness the power of intelligence.
Get ready for a keynote that takes you on a thrilling journey, exploring the vital role of smarter solutions in the design and verification process. It’s not just about speed, fellow adventurers! We’ll boldly discuss the factors that highlight the limitations of solely relying on speed, all while shining a spotlight on the pressing demand for intelligent EDA solutions. Brace yourselves for a universe of possibilities, where performance optimization and tackling intricate design and verification challenges go hand in hand with intelligent solutions.
Speaker: Abhi Kolpekwar
Title: VP & General Manager
Company: Siemens EDA
Practical applications of machine learning in design verification
ML (Machine Learning) is transforming the way we work in a wide range of industries and this has been accelerated by generative AI (Artificial Intelligence) applications such as ChatGPT. In this presentation we investigate how ML and AI can potentially be applied in DV (Design Verification), from automation of requirements/specification analysis and test plan generation, through test bench creation and test generation, to debug and coverage closure.
There is a very wide range of ML techniques available and this presentation first surveys those techniques and how they have been applied (successfully and unsuccessfully) to DV in both academia and in real projects. The objective is to better understand how to apply the most promising techniques to a wide range of DV activities to ultimately make DV both more efficient and effective.
The main objective of the presentation is to give the audience a better understanding of what is achievable of applying ML in DV and to give practical suggestions on their adoption.
Key takeaways
- Overview of the various ML techniques
- Better understanding of the potential applicability of ML to DV
- Practical advice and experience of applying ML to DV
Speaker: Jagadeesh Jonna
Title: Director- Design & Verification
Company: Tessolve
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