Tutorial 1A: Static Signoff Best Practices – Learnings and experiences from industry use cases

Date: 9/13/2023
Time: 11:45 – 13:15

Verification flows seemingly have an infinite appetite to consume engineering resources. Per a recent case study by Wilson Research Group, design engineers typically spend 46% of their time doing verification. Verification engineers, of course, spend all their time doing verification.

Although the most significant contributor to silicon re-spin is logic or functional bugs, clocking related bugs come a close second. With increased design sizes and ever-increasing complexity in clocking, power management and resets, formal and static methods have become crucial tools to close verification of complex designs.

The tutorial teaches six fundamentals to maximize design and verification efficiency.

The tutorial finally proposes a set of Static Signoff best practices based on industry learnings and experiences.

The tutorial is designed to benefit audience members and enable them to enhance the state of verification practice in their workplace.

Tutorial 2A: Improving Debug Productivity using latest AI & ML Techniques

Date: 9/13/2023
Time: 11:45 – 13:15

Semiconductors have become an integral part of everything that we use or interact with. Generational changes in computing and advent of AI, ML, and other advanced features has caused an explosion in semiconductor usage. All this has been possible because there is constant innovation happening in IP development and Protocol design. As the world becomes more interconnected, ASIC’s for specific applications are going to become even more pervasive. Building complex SoC’s from different IP’s and Protocols is already becoming is huge effort. Verifying these complex systems takes the complexity to another level. Debugging has always been the biggest bottleneck as designs have grown larger.

Traditional methods of debug can help but they are extremely time consuming and resource consuming. Re-running simulations multiple times just to obtain more debug information significantly hampers overall debug performance and throughput.

Designs today use sophisticated object-oriented programming- (OOP-) based testbenches, third-party IP, and embedded software running on many cores. Today’s testbenches are typically created in hardware verification languages (HVLs) like SystemVerilog, e, and SystemC. Test cases are highly randomized with many moving parts. When an issue arises, identifying the origin of the bug can be quite challenging. Is it in the testbench? In the RTL? Or the VIP? A substantial amount of analysis time is needed to understand the “big picture” as well as narrow down the area of the bug prior to identification.

Using the same traditional debug flow that has been used for last 2 decades using post-process register-transfer level (RTL) waveform inspection paired with log files for message analysis leaves the engineer vulnerable to running multiple debug iterations if the right information is not present at the end of each run.Accelerating and improving this Debug is becoming critical and imperative to address the expanding verification challenge. Constant changes happening to the design/TB are also adding debug cycles when things don’t work as expected. Verification Data explosion is becoming a key bottleneck for analysis. We need sophisticated tools to sift through the data being generated and help engineer Root-Cause the failure faster.

Using latest AI / ML techniques we can shorten the debug cycle significantly. If the tools can intelligently point out where an engineer should start debugging to accelerate the debug process, it significantly improves the verification engineer’s productivity. If tools could point out where the source code changed, who made the change and how it is affecting the functionality it gives engineer significant advantage to root-cause bugs faster and have much more efficient verification.

Join this tutorial to see and understand how we apply Apps which are using the AI / ML techniques to address this verification challenge and how it can shorten the overall debug cycle significantly.

Tutorial 1B: Taking the first steps towards verifying billion gate designs with formal methods

Date: 9/13/2023
Time: 16:00 – 17:30

We are standing at unprecedented crossroads. Semiconductors are powering up the fastest innovation in human history due to the demands of machine learning/AI. Modern-day cars have more processors than some of the modern aeroplanes. We want the cars, phones, and computers to be ultra-modern and intelligent and at the same time we would like them to be energy-efficient, safe and secure. Semiconductors growth drivers – AI, automotive, 5G/6G, cloud/data, memory and storage are driving innovation at a pace that is unmatched in human history breaking barriers with new advanced open-source processor designs, advancement in 5G/6G technologies, chiplets, and NoCs.

Determining functional correctness is the most important requirement in any test & verification, not to recognize that safety & security are now gaining equal attention while engineers struggle to meet the performance and power, and area requirements (PPA).

Simulation is the main workhorse in the industry. Together with FPGA and emulation it relies on using stimulus and coverage for closure. Formal verification is the only way of establishing proofs of correctness via a mathematical proof. Formal methods come in many flavours – theorem proving, property checking, and equivalence checking. Property checking remains the most popular form of formal methods; its true scope and application is massively hindered by the lack of know-how in methodology.

This tutorial introduces formal verification and will show how to master the concepts of abstraction and formal coverage to obtain efficient results with formal property checking including bug hunting and exhaustive proofs. Aided with examples throughout, it will provide the learner with enough insights to explore further advanced learning in the application of formal methods for large-scale design verification.

Tutorial 2B: Fast track RISC-V System Validation Using Hardware Assisted Verification Platforms

Date: 9/13/2023
Time: 16:00 – 17:30

As we enter the third decade of the 21st century, several advances in the semiconductor and computer industries have caused an explosion of computational and silicon architectural exploration and discovery.

These advances—the introduction of Artificial Intelligence (AI) functionality, faster communications with 5G, and the deployment of sensors into all types of applications generating masses of data—are causing a dramatic rise in device and system complexity with a corresponding increase in design complexity. The system complexity includes hardware and software design and development. Verification of such a complex system is challenging.

RISC-V based SOC market is expected to grow rapidly at the CAGR of 67%. The software development & validation cost is increasing exponentially. Any verification bugs found may risk re-spin and could even lead to delay in products launch.

This tutorial educates users on how FPGA based verification could be adopted in the design cycle for a typical RISC-V SOC. The tutorial also highlights some of the challenges faced and will go deep into how Synopsys HAPS Prototyping solutions helps in accelerating software development, hardware verification, system validation from individual IP blocks to processor subsystem to complete SOC.

This tutorial would cover step by step guide on how such a RISC-V SOC could easily prototype with Synopsys HAPS Prototyping solutions. It would also demonstrate how to validate real world interface and enable hardware software validation.