Short Workshop 3A_1: Accellera’s Latest Updates and a Look Forward

Date: 9/13/2023
Time: 11:45 – 12:30

Lu Dai, Accellera Chair, will highlight current working group activities such as those from the Portable Stimulus Working Group to bring the latest updates to the standard to the community.

The fast-paced efforts of the newest working group focused on defining:

• A standard Clock Domain Crossing collateral specification and much more from Accellera’s active working groups.
• He will also discuss the upcoming meeting at the end of September for a Proposed Working Group focused on Federated Simulation.

Short Workshop 3A_2: Advanced Core/SoC Verification for RISC-V and Other Cores

Date: 9/13/2023
Time: 12:30 – 13:15

Processor core verification represents an array of complex challenges. With the advent of RISC-V, new issues have emerged, which add to this complexity. Whether you are a processor developer working on a RISC-V or other core, or an SoC integrator incorporating one of these new processors, the learning we will provide in this workshop will add to your arsenal of verification techniques.

Breker has been working with multiple RISC-V vendors and users. We have discovered that tests used to ensure the smooth integration of these processors into SoCs, both large and small, may also be applied to cores under development in unique ways to drive increased quality. For example, interrupt testing at the SoC level may also be applied to the core to ensure the smooth handling of the operational interrupt. Load Store mechanisms at the SoC level may be introduced at the core level to understand if the device can be tripped up. Will the RISC-V memory protection be enough to ensure security at the SoC level? Of course, for multiple core or application devices, full system coherency becomes a critical component.

What are the algorithms that may be effectively used to provide these tests? How do you ensure full coverage of multi-faceted tests? How can you torture test the core and SoC to tease out complex, hard to predict corner cases in which might lurk a bug or an operational bottleneck? All of these questions will be answered during this workshop.

Short Workshop 4A_1: Identifying and overcoming Multi-Die System Verification Challenges

Date: 9/13/2023
Time: 11:45 – 12:30

The economics of packing more functions onto a single chip is driving multi-die system designs. Multi-die systems offer several advantages in terms of performance, functionality, power efficiency, package size, reliability, and design flexibility, making them a popular choice for advanced electronic systems like high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), autonomous vehicles, mobile, and hyperscale data centers.

The Universal Chiplet Interconnect Express (UCIe) standard was introduced in March of 2022 to help standardize die-to-die connectivity in multi-die systems. UCIe can streamline interoperability between dies on different process technologies from various suppliers.

However, multi-die system complexity drives the need for high quality verification process by utilizing protocol verification IPs and hardware-assisted verification solutions to achieve great levels of quality in SoCs. The tutorial will discuss those challenges and describe how to efficiently overcome them.

Short Workshop 4A_2: Accelerating heterogeneous SoC designs with prebuilt blueprints and cloud hardware assisted emulation and prototyping

Date: 9/13/2023
Time: 12:30 – 13:15

Chip designs are increasingly multi-ISA and heterogeneous. The rise of RISC-V / open source hardware and recent interests around AI and edge computing are opportunities for IP and EDA vendors. The value proposition of the future for customers would be a holistic system solution (HW & SW & EDA design flow) that is the closest to their end-product and design flow at the lowest possible costs.

Siemens EDA and SoC.one have partnered to provide IC-XploR, a cloud-native offering that enables developers with on-demand, low-friction access to feature rich design environment consisting of EDA tools and hardware, compiler toolchain, operating systems, and sample applications that utilize and show-case commercial and open source ISA from different sources and vendors.

As part of IC-XploR, highly integrated reference designs called blueprints are made readily available to be onboarded on Siemens EDA prototyping and hardware-assisted verification platforms. IC-XploR blueprints target high-growth verticals including wireless communication, cybersecurity, AIoT, AI/ML and automotive.

Short Workshop 3B_1: Automation of Realisation Layer for IP/SoC using PSS & SystemRDL

Date: 9/13/2023
Time: 16:00 – 16:45

The PSS (Portable Stimulus Standard) is a comprehensive language comprising two primary layers: the Modeling layer and the Implementation layer. In the latest version, PSS 2.0, the concept of Registers and Sequences has been introduced, allowing for more precise definition and control of the system behavior.

The Realisation layer encompasses various elements such as Functions, Registers, and Sequences, among others, to accurately represent the behavior of the system being modelled. We leverage both SystemRDL and PSS languages to generate a complete model. By combining the capabilities of these languages, we can produce a comprehensive representation of the system, covering both the register-level details and the high-level system behavior.

SystemRDL allows users to provide register information, specifying the registers’ characteristics and properties. On the other hand, PSS is used to define the system behavior and sequences, outlining the desired steps and actions to be performed. By combining these two languages, we enable users to capture both the structural aspects of the system (using SystemRDL) and the dynamic behavior (using PSS) to generate a complete and accurate representation.

From this declarative specification we show how to generate multiple output formats for different domains, including UVM sequences for verification, SystemVerilog sequences for validation, C code for firmware and device driver development, and documentation outputs like HTML and flowcharts.

The tests generated through this process are in the form of UVM sequences for simulation purposes and firmware sequences for hardware/software co-simulation and post-silicon validation. These test sequences encompass various system operations, such as start-up sequences, read-write operations, shutdown sequences, low power mode sequences, and more.

This workshop will introduce the two Accellera languages and juxtapose with each other and IP-XACT. It will show the attendees the benefits and pitfalls of each of these standards. A preferred methodology for development of IP/SoC and their integration will be presented. The target audience will be Architects, Designers, Verification Engineers, Firmware and Validation Engineers.

Short Workshop 3B_2: CXL Verification using Portable Stimulus

Date: 9/13/2023
Time: 16:45 – 17:30

Compute Express Link (CXL) is an open industry standard that offers high-bandwidth and low-latency connectivity between a host processor and PCIe devices – including accelerators, memory and smart I/O. CXL is poised to meet the demands of high performance work-loads in Artificial Intelligence, communication systems and HPC.

In this workshop, we will share our experience in creating Portable Test and Stimulus Standard (PSS) models for verifying CXL type 3 devices.

Short Workshop 4B_1: An Overview of Ethernet 10Base-T1S in Automotive SoCs and its Verification

Date: 9/13/2023
Time: 16:00 – 16:45

Automotive industry is one of the markets which relies on high performance, efficiency, and quality of semiconductor solutions. Day-to-day there are enhancements happening in the auto-tech where OEMs and Tier-1s are trying to improve performance of vehicles by growing the number of sensing peripherals.

Increase in number of peripherals pushing the demand for advanced SoC architecture which enriches the automotive eco-system with capabilities like AI/ML, image processing, digital twin, V2X communications and many more.

SoC providers are working towards advancing their products by adapting the latest and trending protocols. One of the key protocols that plays a crucial role in subsystem and system level communication in Automotive applications is Ethernet. A fast-evolving protocol, rising need of faster and secure data transmission propelling the demand for advanced specifications and features.

As in-vehicle electronics grow in volume and complexity to support the goal for autonomous driving, 10Base-T1S Automotive ethernet used to enhance In-Vehicle Network architecture. 10BASE-T1S is targeted for Automotive industry, developed with an objective to achieve collision free, deterministic transmission on a multi-drop network. This single twisted pair technology boasts lighter weight and lower costs, while meeting stringent automotive EMC requirements. 10BaseT1S protocol is used for connecting sensor, microphones and speakers to power train, car body and infotainment Engine Control Units. It allows the integration of diverse sensors into an automotive-Ethernet system and opens the door for new opportunities in Ethernet communication.

In this tutorial Synopsys and STMicroelectronics jointly presents and focus on:

• Automotive SoC design types and use cases
• Importance of Ethernet 10BaseT in Automotive SoC
• Challenges of 10BaseT verification at SoC level
• Solutions to address SoC verification needs
• STMicroelectronics’ success with Synopsys Verification IP

Short Workshop 4B_2: UCIe based Design Verification

Date: 9/13/2023
Time: 16:45 – 17:30

The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine Chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. This has opened gateway to sophisticated RTL designs related but not limited to management of PCIe, CXL and Streaming protocol traffic, a new Physical Layer, and a convoluted Die-to-Die adapter. Hence, the verification topologies of such designs have exponentially increased.

In this workshop, we will investigate effective strategies to optimize effort and improve productivity in the verification using Chiplet-like reusable verification components.

Using Cadence UCIe VIP, you will get a hands-on experience of:

a) Integration of a various UCIe blocks with a DUT
b) Configuration
c) Write and Run a Basic Test case
d) Debug using Smart Log, Packet Tracker, and Waveform debugger