KEYNOTES

The Increasing Verification Horizon in the Era of Pervasive Intelligence

Artificial Intelligence (AI) is driving the transformation of the systems and semiconductor architectures, raising the stakes for verification. The horizon for verification expands beyond the traditional functional verification to include a wide range of metrics to support AI on the edge or in datacenters, from training to inferencing all the way to generative AI.

This keynote presentation will explore why achieving the target metrics needs to start at the architectural stage, especially for multi-die designs. Vikas Gautam (Synopsys) and Subrangshu Das (Google) will discuss how to best utilize hardware-assisted verification solutions crunching complex AI workloads to achieve optimal performance and power metrics. They will also provide their perspectives on how built-in debug is a critical component of silicon lifecycle from pre-silicon to in-field deployment. The session will wrap up with their insights on implementing security as an essential expansion of the verification horizon for any state-of-the-art system.

Speaker: Vikas Gautam
Title: VP Engineering
Company: Synopsys

Speaker: Subrangshu Das
Title: Director
Company: Google Silicon

Accelerated Infrastructure in an AI World

AI and ML are poised to transform our personal and professional lives. But for AI to succeed, we need to develop an accelerated infrastructure that can both keep pace with the rising bandwidth and performance demands of AI applications while keeping a lid on power latency, and cost. And that means rethinking the vast portfolio of silicon devices that make up infrastructure along with developing entirely new categories of chips.

Puneet Agarwal, Vice President and CTO of Data Center Switching at Marvell, will outline what’s driving the growth of AI, the technologies being developed to fulfill its promise, and the role India will play in developing the accelerated infrastructure.

Speaker: Puneet Agarwal
Title: VP & CTO, Data Center Switching
Company: Marvell

AI for Verification – Today’s Reality Vs. Tomorrow’s Promise

Artificial intelligence, machine learning, large language models, and similar technologies and approaches have been constantly promoted as world- changing over the past several years. IC design and verification teams and EDA suppliers continue to search for the ‘killer app’ that will leverage AI. This presentation will examine what AI solutions are available now for efficiency and debugging, what’s on the near-term horizon, and what potential still lies ahead.

Speaker: Matt Graham
Title: Product Management Group Director
Company: Cadence

The Future is Formal

Formal methods are the way to go! Formal methods, just like AI, have also taken several decades to take off, but they surely have! Industry reports that nearly a third of digital designs undergo formal property verification. Formal is the only way to establish exhaustive proofs of bug absence and absence of deadlocks and livelocks. Formal adoption has been limited due to the challenges in understanding how to overcome proof convergence required for complete sign-off with the right combination of innovations in methodology and automation – every design block is verifiable with formal.

This talk will cover the exciting trajectory of formal methods and describe how they can be used and deployed to make everyone adept in formal paving way to get the best ROI for all kinds of chips, hunting down bugs from the first hour of design bring up all the way to high-assurance sign-off through six-dimensional coverage. Formal would become indispensable for high-quality sign-off in the next decade, and those semiconductor players who could adopt formal would successfully continue to shape the future.

Speaker: Ashish Darbari
Title: Founder & CEO
Company: Axiomise

Navigating the Future of Chip Design Verification in an Era of Rapid Semiconductor Innovation

The semiconductor industry is on the cusp of a transformative era, propelled by relentless technological advancement and soaring market demands. As chip designs venture into the sub-nanometer realm (7nm, 5nm, 3nm+), their complexity grows exponentially, making design verification a formidable hurdle. The need to validate multiple use cases for each product, coupled with the industry’s relentless drive for faster time-to-market, amplifies the pressure on verification teams. Ensuring product quality amidst these challenges requires innovative approaches to accelerate verification while maintaining stringent reliability standards. This presentation delves into the critical role of verification in modern chip design, examining the industry’s evolving needs and the breakthroughs necessary to navigate this complex landscape.

Speaker: Apurva Kumar
Title: Director – Semiconductor Vertical
Company: Quest Global

PLATINUM KEYNOTE

Smart Verification: Faster is not enough!

Buckle up, fellow tech explorers! The ever-changing landscape of semiconductor design is calling for a cosmic paradigm shift in how we conquer upcoming verification challenges. Sure, we’ve zoomed towards faster and more efficient verification methodologies thanks to tech wizardry, but we can’t warp past the fact that sheer speed alone won’t guarantee us complete solutions. As we reach for new frontiers, the complexity of design and verification tasks skyrockets, beaming us towards an urgent need to harness the power of intelligence.

Get ready for a keynote that takes you on a thrilling journey, exploring the vital role of smarter solutions in the design and verification process. It’s not just about speed, fellow adventurers! We’ll boldly discuss the factors that highlight the limitations of solely relying on speed, all while shining a spotlight on the pressing demand for intelligent EDA solutions. Brace yourselves for a universe of possibilities, where performance optimization and tackling intricate design and verification challenges go hand in hand with intelligent solutions.

Speaker: Abhi Kolpekwar
Title: VP & General Manager
Company: Siemens EDA

PLATINUM KEYNOTE

Practical applications of machine learning in design verification

ML (Machine Learning) is transforming the way we work in a wide range of industries and this has been accelerated by generative AI (Artificial Intelligence) applications such as ChatGPT. In this presentation we investigate how ML and AI can potentially be applied in DV (Design Verification), from automation of requirements/specification analysis and test plan generation, through test bench creation and test generation, to debug and coverage closure.

There is a very wide range of ML techniques available and this presentation first surveys those techniques and how they have been applied (successfully and unsuccessfully) to DV in both academia and in real projects. The objective is to better understand how to apply the most promising techniques to a wide range of DV activities to ultimately make DV both more efficient and effective.

The main objective of the presentation is to give the audience a better understanding of what is achievable of applying ML in DV and to give practical suggestions on their adoption.

Key takeaways