September 10-11, 2025

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. This year, DVCon India is expanding its focus to increase participation from universities and organizing a hackathon.

This invite for the hackathon, titled Accelerating AI on FPGA presents some unique opportunities for students:

1. To dabble in the basics of machine learning
2. To meet some subject matter experts from across academia and industry
3. To implement your very own ML engine on an industry standard FPGA platform
4. To win cash prizes and intern at leading-edge VLSI companies

The hackathon is to be conducted completely virtually in two stages:

Stage 1:

– Problem statement whose solution will only be simulation-based.
– Teams will be given three weeks to submit proposals describing their solutions.
– The evaluation metrics will be published along with the problem statement.
– The submissions describing the proposed solutions will be judged to select the teams
who will move to stage2.

Stage 2:

– The solution of this stage will involve implementation on an FPGA cloud.
– Teams will have 48 hours to get to the solution.
– Evaluation metrics will be published along with the problem statement.