September 10-11, 2025

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.

This invite for the design contest, titled “VEGA microprocessor (RISC-V) based Design & Verification Challenge” presents some unique opportunities for academic students:

1. Achieve deeper understanding of RISC-V architecture, indigenous VEGA Microprocessor and ecosystem.
2. Explore the design and verification space for better performance.
3. Implement your own AI hardware accelerator on industry standard FPGA in the areas such as Robotics, Healthcare, autonomous driving, sports tech, smart transportation and any other innovative application of AI
4. Opportunities to interact with experts from industry and academia.
5. To win cash prizes and potential intern opportunities at leading-edge VLSI and sponsor companies

VEGA is a series of high-performance processors including India’s first indigenous 64-bit multi- core RISC-V based Superscalar Out-of-order Processor, developed by C-DAC as part of the Digital India RISC-V (DIR-V) program by the Ministry of Electronics and Information Technology (MeitY), Govt. of India. These high-performance processors are based on the open-source RISC-V Instruction Set Architecture with Multilevel caches, Memory Management Unit and Coherent Interconnect. Six processors are currently available in the VEGA series, 32- bit Single Core 3-stage In-order, 32-bit Single Core 5-stage In-order, 64-bit Single Core 6-stage In-order, 64-bit Single Core 16-stage Out-of-Order Superscalar, 64-bit Dual Core 16-stage Out- of-Order Superscalar and 64-bit Quad Core 16-stage Out-of-Order Superscalar. These indigenous microprocessors employing the state-of-the-art architecture have a performance which is at par with other commercially available processors. The microprocessors are available as soft IPs and are amenable/ customizable for better performance/power targeted for various strategic/industrial/commercial applications.

The design contest is to be conducted virtually:

• Problem statement solution will be based on RTL Design, Functional verification, and implementation on an FPGA.
• Each team with maximum of 3 members should register and will be given four months with specific milestones for completion in multiple stages.
• The milestone details will be published along with the problem statement.
• There will be mentoring sessions at different milestones during the contest duration.
• Remote access to Genesys 2 FPGA Board and simulator/synthesizer will be provided

Congratulations to Design Contest Stage 2A winners!