September 10-11, 2025

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.

This invite for the design contest, titled C-DAC’s VEGA microprocessor (RISC-V) based Design & Verification Challenge presents some unique opportunities for academic students:

1. Achieve deeper understanding of RISC-V architecture, VEGA Microprocessor and applications.
2. Explore the design and verification space for better performance.
3. Implement your very own processor core on industry standard FPGA!
4. Opportunities to interact with experts from industry and academia.
5. To win cash prizes and internship at leading-edge VLSI companies

VEGA series of high-performance processors are developed by C-DAC as part of the DIR-V program and is based on the open-source RISC-V Instruction Set Architecture with Multilevel Caches, Memory Management Unit and Coherent Interconnect.

The design contest is to be conducted virtually:

• Problem statement whose solution will be based on RTL Design, Functional verification, and implementation on an FPGA.
• Each team with maximum of 3 members should register and will be given four months with specific milestones for completion in two stages.
• The milestones/ evaluation metrics will be published along with the problem statement.
• There will be mentoring sessions at different milestones during the contest duration.

Congratulations to Design Contest Stage 2A winners!