Posters
| ID | Company | Authors | Title |
|---|---|---|---|
| 709 | RGKUTN | Karamalaputti Rahul, Gandham Nagaraju, Moyya Chandinee, Shyam Peraka and Reddy Sudheer | AUTOMATED FLOATING TRASH COLLECTING BOAT |
| 1300 | TCS | Ambati Rajashekar, Pranjit Das, Avi Kumar Shrivastava and Partha Acharya | Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM Hardware. |
| 3634 | QUALCOMM | Ravindrareddy Pulicharla, Nitin Neralkar, Chayan Pathak, Venkatesh Chepuri, Madhusudhan Koothapaakkam, Sourabh Bhattacharjee and Piyush Upadhyay | Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV |
| 3653 | RGKUTN | Shyam Peraka, Reddy Sudheer, Venu Pabbuleti, Mangaraju Tharun Kumar and Jagu Naveen Kumar | DIGITAL EYE FOR AID OF BLIND PEOPLE |
| 4336 | INTEL | Pravat Kishor Nayak, Vikrant Kapila, Pushpa Naik and Niketkumar Sharma | Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design |
| 4621 | CADENCE | Kiran Kumar Indrakanti and Sai Asrith Tabdil | How to make debug more efficient in day-to-day life using Indago |
| 4968 | QUALCOMM | Prashant Hota and Shekhar Jha | Accelerating SOC Verification, Reducing Simulation Turnaround Time & Diskspace Optimization using Dynamic Test Reload (DTR) |
| 4989 | SAMSUNG | Sougata Bhattacharjee | Counterintuitive approaches to have better communication between UVM and Python for registers with Single controlling algorithm |
| 5048 | SAMSUNG | Amitayu Banerjee, Subramanian Ravichandran and Sekhar Dangudubiyyam | Highly Flexible Robust System Level HW-SW Power Management Verification Based on RISC-V |
| 6264 | NXP | Shweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharvanan and Kavya P S | Design verification of a cascaded mmWave FMCW Radar |
| 6566 | "1. SIEMENS 2. NXP Semiconductors" | Manish Bhati(Siemens) , Rajagopal Anantharaman (Siemens) and Inayat Ali (NXP Semiconductors) | Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics |
| 7092 | INTEL | Sudhanshu Srivastava, Himani Jawa, Sini Balakrishnan and Nishant Raman | Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations |
| 8189 | AGNISYS | Nikita Gulliya and Sudhir Bisht | Automation of Realization Layer for IP/SoC using PSS 2.0 and SystemRDL |
| 8630 | SAMSUNG | Vinay Swargam, Sriram Kazhiyur Sounderrajan and Lakshmana Kumar A | A Reconfigurable and Fully Automated SRAM Environment Generation Flow for Robust Verification and to Accelarate DV Closure |
| 9314 | SYNOPSYS | Amit Kumar and Shobhit Shukla | Faster Elaborations with Cloud Storage |
| 9800 | SIEMENS | Sai Jagadeesh Ambati, Sulabh Kumar Khare and Atul Sharma | Advanced specification driven methodology for quick and accurate RDC signoff |
| 9180 | SAMSUNG | Vivek Kumar, Manish Mallan and Karthik Majeti | Securing design confidence for Low power and Functional features of Image Sensor SOC - Reuse of UVM simulation testbench on HW acceleration platform |
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