September 10-11, 2025

Short Workshop 3A_1: Find and Fix Excessive Power Dissipation of your Chip Very Early in the Design Cycle

By: Manish Pandey, Siemens

Designers face enormous challenges for low-power designs. Whether IoT at the edge, AI in the datacenter, robotics, or ADAS, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every chip design stage, including performance, reliability, and packaging. Waiting to address power until late in the design cycle – post-netlist or during physical implementation – can be extremely costly. The design may overrun the power budget, overheat, or have long-term reliability issues that cannot be addressed at the gate level, layout, or package selection. The best point in the design cycle to address power is at the beginning during the architectural and RTL stages. The earlier power analysis and optimization start, the more likely a chip will meet its power objectives.

Short Workshop 3A_2: Power Dynamics: Shaping the Future of the Data-Centric Era

By: Vijay Chobisa and Gaurav Saharawat, Siemens

As the data-centric era continues to evolve, the demand for high-performance computing and advanced data processing grows exponentially. At the heart of this transformation is the semiconductor industry, where power consumption has become a critical factor in shaping the future of technology. This presentation explores the role of power dynamics in driving the next wave of innovation in the data-centric era. We will delve into the challenges and opportunities presented by the need to balance performance with energy efficiency in semiconductor design. Key topics include advancements in power analysis and estimation, and the impact of power consumption on data centers. By understanding the intricate relationship between power consumption and technological advancement, we can unlock new possibilities for sustainable growth in a world increasingly defined by data.

Short Workshop 4A_1: What’s new in SystemC 3.0 – IEEE 1666-2023 Challenges

By: Aravinda Thimmapuram, CircuitSutra

This workshop covers the new features of the latest version of SystemC, ie.. SystemC 3.0 as per the standard IEEE 1666-2023.

SystemC is a language of choice for developing the simulation models of semiconductor chips & electronics systems at an abstraction level above RTL. It enables advanced shift-left ESL methodologies by allowing certain operations which are not feasible in traditional RTL to GDS design flow – pre-silicon software development, architecture exploration & optimization, hardware-software codesign, high-level synthesis, software driven verification of SoC, etc..

SystemC started in 2000 by the formation of an industry alliance Open SystemC Initiative (OSCI). It got ratified as an IEEE standard IEEE 1666-2005 in 2005, the next version of the standard was IEEE 1666-2011. Recently the latest version of the standard is released as IEEE 1666-2023

Accellera has released the reference simulator implementation SystemC “3.0”, compliant with the IEEE 1666-2023 towards the end of 2023. SystemC 3.0 has new features and enhancements targeted towards functional improvements and increasing productivity. This short workshop from CircuitSutra introduces the audience to SystemC 3.0 and provides an overview of the changes.

The target audience of this workshop are the professionals involved in the SystemC modelling, SoC architects, project managers and other decision makers involved in deciding the semiconductor design roadmap in their companies. It may also be useful for the professionals who want to get started with SystemC based shift-left methodologies.

Short Workshop 4A_2: Harnessing AI for Enhanced Verification Efficiency

By: Anika Sunda – Cadence, Sundararajan Ananthakrishnan – Cadence, Vivekananda Upadyaya P – Qualcomm

Learn how Cadence is harnessing the power of machine learning to improve verification efficiency and productivity with Verisium Artificial Intelligence (AI)-Driven Verification Platform for cutting-edge next-generation IP and SoC verification and debugging.

Short Workshop 2B_1: High Performance Design Verification Techniques

By: Arun Joseph and Chakrapani Rayadurgam, IBM

Hardware verification stands as a pivotal and resource-intensive component of the entire hardware design cycle, accounting for approximately 50-70% of the total design development effort. Scalable hardware verification has encountered numerous challenges while also seizing opportunities to refine its methodologies and technologies, necessary to tackle the increasing complexity of hardware designs. We outline the evolution of hardware verification, emphasizing the growing automation within the process, especially in the context of high-performance, enterprise-class, hardware designs like IBM POWER10, and Telum microprocessors. Subsequently, we focus some of the current challenges and explore how emerging opportunities from machine learning, artificial intelligence, and data science can further propel the evolution of next generation hardware verification.

Short Workshop 2B_2: Portable Stimulus and VIP: Like a Hand in a Glove

By: Raghavendra HM & Manoj Manu, Siemens

The Portable Stimulus Standard (PSS) encourages verification engineers to focus on describing test scenarios, without worrying about the underlying target environment on which the test will ultimately be run. By describing the scenarios in terms of a randomizable schedule of actions, or behaviours that will execute, the test can easily be retargeted to different implementations for different environments. Especially at the block- and subsystem-level, these target environments will usually be UVM environments, often incorporating standard-protocol VIP components. The ability to reuse a PSS test scenario across multiple environments, including using different VIP to execute the same actions, is one of the main definitions of the “Portable” part of PSS. This session will show how to define a PSS model that can be retargeted at different VIP components to allow the same scenario throughout your development flow. In addition, the Siemens UVM Framework makes it easy to assemble UVM environments that include VIP and other components and create the infrastructure to execute the PSS scenarios in the UVM environment.

Short Workshop 3B_1: Functional Safety and High reliability in FPGA design

By: Nilesh Shilankar, Manohar Reddy Vadicherla, Synopsys

Ensuring functional safety and achieving high reliability are critical aspects of modern electronics system design, particularly in safety-critical industries such as automotive, aerospace, and medical devices. Synopsys Synplify®, a leading synthesis software, plays a pivotal role in meeting these stringent requirements by providing advanced features and methodologies tailored for functional safety and high reliability designs.

This workshop will explore the integration of Synplify into the development workflow for functional safety and high reliability applications. It will discuss key capabilities such as advanced synthesis optimization, comprehensive safety checks, and support for industry-standard safety standards like ISO26262 and IEC 61508. This session will highlight the use of verification techniques and robust error handling mechanisms within Synplify to detect and mitigate potential hazard early in the design process.

Short Workshop 3B_2: FPGA Prototyping for Large Multi-Die/Multi-Core Designs

By: Madhav Chikodikar, Subhankar Ghosh, Synopsys

Today’s design size and complexity continue to increase putting greater pressure on meeting compile time and performance goals of the prototype. Together, they are increasing faster than the available compute capability. This has led to more challenging implementation problems and longer, unpredictable bring-up times for prototypes. To decouple design sizes and compute capacity, a divide-and-conquer approach is needed. This approach helps to enable parallelism.

This workshop will present enhanced capabilities in Synopsys HAPS ProtoCompiler that can enable parallelism – allowing different teams to solve implementation challenges independently and concurrently. In addition, we will discuss how parallelism enables reuse of such implementations for design types involving multi-cores which are often replicated, ultimately reducing peak compute requirements and leading to faster tool execution times. This modular design approach is a framework that will address these needs while also providing a path to faster incremental TaT.

Short Workshop 4B_1: Efficient RISC V Compute Platforms for Enabling the AI Revolution

By: Sujay Deb, IIIT-D for Aarfive Designs

Machine learning based AI algorithms are computationally intensive and need to deal with a large amount of data. This along with slowing of Moore’s law imposes various challenges for the hardware implementation of these algorithms. To meet the high computing demand of Deep Neural Networks (DNNs), designs with many-accelerators are proposed. These designs revolve around achieving high parallelization, efficient memory hierarchy, addressing communication challenges etc. In this talk we will:

• Highlight the steps and strategies that need to be adopted for designing the optimized RISC V SoC hardware platform
• Get an overview about how to design accelerator rich systems and optimally use the shared resources.
• Address the on-chip communication bottlenecks.

Short Workshop 4B_2: Emergence of DIR-V and VEGA Processor Ecosystem

By: Libin T T, CDAC

The workshop on the “Emergence of DIR-V VEGA Processor and Ecosystem” will delve into the advancements and opportunities associated with this cutting-edge RISC-V based architecture developed under India’s Digital India initiative. It will highlight the growing popularity of the DIR-V VEGA Processor, fueled by government support, industry adoption, and educational integration. Attendees will explore the processor’s design and verification aspects, focusing on its performance, energy efficiency, and rigorous verification methods. Additionally, the session will cover the supporting software ecosystem, including development tools, operating systems, and middleware, as well as the role of developer communities and industry groups. Join us to gain a comprehensive understanding of how the DIR-V VEGA Processor is driving technological innovation in India and discover the tools and resources available for engaging with this transformative technology.