September 10-11, 2025

Tutorial 1A: Expanding role of Static Signoff in Verification Coverage

By: Vikas Sachdeva, Real Intent
Date: 9/18/2024

Simulation-based testing has been the go-to approach for checking nearly everything through targeted tests in the ever-evolving verification methodologies. Its effectiveness has been undeniable and continues to play a critical role in the verification landscape. However, it has its limitations. The number of possibilities it can cover remains limited compared to the complete set of potential behaviours, regardless of the number of tests or clever techniques used.

Today, static verification has become an indispensable companion to simulation, formal methods, and other verification techniques, excelling in various specific applications. Its scope has expanded beyond traditional timing analysis, linting, and clock domain crossing (CDC) checks. This expansion has been made possible by the continuous advancements in the power and versatility of static tools and the growing complexity of modern designs. Some verification challenges previously addressed by throwing more resources, such as people, licenses, and machines at the problem, have now surpassed the capabilities of conventional methods for confident signoff.

This tutorial explores several emerging static signoff technologies and their applications in verification flows across large and small design and verification organizations. These technologies shape how various companies approach verification coverage, offering valuable insights and efficiencies that complement existing methodologies.

By leveraging static verification’s strengths alongside other verification techniques, engineers and organizations can enhance their verification coverage, ensuring robust and reliable designs in the face of increasing design complexity. As the field evolves, staying up-to-date with the latest static signoff advancements will be crucial in maintaining a competitive edge in the semiconductor industry.

Tutorial 2A: Next-Generation Debug with Verification Management and IDE

By: Prasad Chelur, Rohit Ohlayan, Synopsys

This tutorial presents an overview of the recently unveiled, cutting-edge advancements in the next-generation Synopsys Verdi® platform. Learn about the power of AI-driven debug and new root cause analysis engines designed to speed-up bug finding, while experiencing enhanced usability through a refreshed graphical user interface. In addition, this session will cover how you can access an integrated development environment (IDE) and a robust verification management system, integrated to boost productivity your verification workflows. Dive into state-of-the-art verification with us as we showcase these groundbreaking capabilities poised to redefine the landscape of verification and debug methodologies.

Tutorial 1B: Accellera Tutorial: Bridging the Gap: Standardizing CDC and RDC Closure with Interoperable Abstract Models

By: Manish Bhati, Suman Chalana, Devender Khari, Jebin Mohandas, Ashish Soni

CDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC’s having 2 trillion+ transistors and chiplet’s having 7+ SOC’s. Today CDC verification has become a multifaceted effort across the chips designed for clients, servers, mobile, automotives, memory, AI/ML, FPGA etc. with focus on cleaning up of thousands of clocks and constraints, integrating the SVA’s for constraints in validation environment to check for correctness, looking for power domain and DFT logic induced crossings, finally signing off with netlist CDC to unearth any glitches and missing crossings during synthesis.

As the design sizes increased in every generation the EDA tools could not handle running flat and the only way of handling design complexity was through hierarchical CDC analysis consuming abstracts. Also, hierarchical analysis helps to enable the analysis in parallel with teams across the globe. Even with all these significant progress in capabilities of EDA tools the major bottleneck in CDC analysis of complex SOC’s and Chiplets is consuming abstracts generated by different vendor tools. Different vendor tool abstracts are seen because of multiple IP vendors, even in house teams might deliver abstracts generated with different vendors tools. The Accellera CDC Working- Group aims to define a standard CDC IPXact model to be portable and reusable regardless of the involved verification tool.

As moving from monolithic designs to IP/SOC with IPs sourced from a small/select provider to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF) are present, the integration can meet the above (quality, speed). However, in areas where standards (in this case, CDC) are not available, most options trade-off either quality, or time-to-market, or both. Creating a standard for inter-operable collateral addresses this gap. This tutorial aims to remind the definitions of CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals and scope of the Accellera CDC Working Group in order to elaborate a specification of the standard abstract model.